| 型號 | 下載 訂購 | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
Quad 2-Input AND Gate Quad 2-Input AND Gate Feature ? Outputs Source/Sink 24 mA 文件:42.68 Kbytes 頁數(shù):7 Pages | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI | ||
Quad 2-Input AND Gate Quad 2-Input AND Gate Features ? Outputs Source/Sink 24 mA 文件:101.53 Kbytes 頁數(shù):7 Pages | RENESAS 瑞薩 | RENESAS | ||
Quad 2-Input AND Gate Quad 2-Input AND Gate Features ? Outputs Source/Sink 24 mA 文件:101.53 Kbytes 頁數(shù):7 Pages | RENESAS 瑞薩 | RENESAS | ||
Quad 2-Input AND Gate Quad 2-Input AND Gate Features ? Outputs Source/Sink 24 mA 文件:101.53 Kbytes 頁數(shù):7 Pages | RENESAS 瑞薩 | RENESAS | ||
Quad 2-Input AND Gate Quad 2-Input AND Gate Features ? Outputs Source/Sink 24 mA 文件:101.53 Kbytes 頁數(shù):7 Pages | RENESAS 瑞薩 | RENESAS | ||
Dual JK Flip-Flop (with Separate Clear and Clock) Description The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. Feature 文件:57.9 Kbytes 頁數(shù):10 Pages | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI | ||
Dual JK Flip-Flop (with Separate Clear and Clock) Description The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. Feature 文件:214.01 Kbytes 頁數(shù):7 Pages | RENESAS 瑞薩 | RENESAS | ||
Dual JK Flip-Flop (with Separate Clear and Clock) Description The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. Feature 文件:214.01 Kbytes 頁數(shù):7 Pages | RENESAS 瑞薩 | RENESAS | ||
Dual JK Flip-Flop (with Separate Clear and Clock) Description The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. Feature 文件:214.01 Kbytes 頁數(shù):7 Pages | RENESAS 瑞薩 | RENESAS | ||
Dual JK Negative Edge-Triggered Flip-Flop Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will p 文件:59.65 Kbytes 頁數(shù):10 Pages | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI |
技術(shù)參數(shù)
- Family.:
HD74AC Series
- Function Gr1:
Gate
- Function Gr2:
NAND Gate
- Function:
Quad. 2-input NAND Gates
- Number of Channel:
4
- Topa[Tjopa] (degC) min.:
-40
- Topa[Tjopa] (degC) max.:
85
- Vcc (V) min.:
2
- Vcc (V) max.:
6.0
- Iout (mA):
±24
- Propagation Delay (ns) max.:
8.5
- Package Type:
SOP
- Production Status:
Non-promotion
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
HIT |
24+/25+ |
850 |
原裝正品現(xiàn)貨庫存價優(yōu) |
詢價 | |||
HITACHI |
25+ |
SOP |
1000 |
強調(diào)現(xiàn)貨,隨時查詢! |
詢價 | ||
HITACHI |
09+ |
SOP16 |
5500 |
原裝無鉛,優(yōu)勢熱賣 |
詢價 | ||
HIT |
17+ |
TSSOP |
6200 |
100%原裝正品現(xiàn)貨 |
詢價 | ||
HITACH |
25+ |
SOP20 |
18000 |
原廠直接發(fā)貨進口原裝 |
詢價 | ||
HIT |
23+ |
SOP |
7000 |
絕對全新原裝!100%保質(zhì)量特價!請放心訂購! |
詢價 | ||
HITACHI |
24+ |
SOP |
6980 |
原裝現(xiàn)貨,可開13%稅票 |
詢價 | ||
RENESAS |
2016+ |
SOP |
3000 |
只做原裝,假一罰十,公司可開17%增值稅發(fā)票! |
詢價 | ||
HITACHI |
00/01+ |
SOP16 |
670 |
全新原裝100真實現(xiàn)貨供應(yīng) |
詢價 | ||
HIT |
2015+ |
SOP14 |
19889 |
一級代理原裝現(xiàn)貨,特價熱賣! |
詢價 |
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