Digital FET, P-Channel

General Description This P-Channel logic level enhancement mode field effect transistor is produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for

文件：63.55 Kbytes 頁數(shù)：4 Pages

FAIRCHILD

仙童半導(dǎo)體

Digital FET, P-Channel

ONSEMI

安森美半導(dǎo)體

絲?。?a target="_blank" title="Marking" href="/.39k/marking.html">.39K；Package：SOT-23；P-Channel Mosfet

Product Summary ? Voss= 20V, Ip=-07A + Ros(on) [email protected] Max) [email protected] (Max) 950mQ @-1.8V(TYP)

文件：1.50903 Mbytes 頁數(shù)：4 Pages

TECHPUBLIC

臺舟電子

Digital FET, P-Channel

General Description This P-Channel logic level enhancement mode field effect transistor is produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for

文件：63.55 Kbytes 頁數(shù)：4 Pages

FAIRCHILD

仙童半導(dǎo)體

數(shù)字 FET，P 溝道，-25V，-0.12A，10Ω

這些P溝道邏輯級增強模式場效應(yīng)晶體管采用了飛兆半導(dǎo)體專有的高單元密度、DMOS技術(shù)。 這種密度非常高的工藝是專為最大限度地降低導(dǎo)通阻抗而定制的。 該器件特別為低電壓應(yīng)用設(shè)計，以替代數(shù)字晶體管。 由于不需要偏置電阻，該P溝道FET能替代一些具有不同偏置電阻的數(shù)字晶體管，如DTCx和DCDx系列。 ?-25V、-0.12A（連續(xù)值）、-0.5A（峰值） RDS(ON) = 13 Ω @ VGS= -2.7 V、RDS(ON) = 10 Ω @ VGS = -4.5 V。\n?柵極驅(qū)動電平要求極低，從而可在3V電路中直接運行。 VGS(th) < 1.5V。\n?柵-源齊納二極管增強耐靜電放電(ESD)能力。 >6kV人體模型。\n?緊湊型工業(yè)標(biāo)準(zhǔn)SOT-23表面貼裝封裝。\n?用一個DMOS FET替代多個PNP數(shù)字晶體管（DTCx和DCDx）。;

ONSEMI

安森美半導(dǎo)體