20-Bit, 40 MSPS, Differential SAR ADC

GENERAL DESCRIPTION The AD4080 is a high-speed, low noise, low distortion, 20-bit, Easy Drive, successive approximation register (SAR) analog-to-digital converter (ADC). Maintaining high performance (signal-to-noise and distortion (SINAD) ratio > 90 dBFS) at signal frequencies in excess of 1

文件：3.63552 Mbytes 頁數(shù)：95 Pages

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Evaluating the AD4080 20-Bit, 40 MSPS, Differential SAR ADC

FEATURES ? Full featured evaluation board for the AD4080 ? Analysis | Control | Evaluation (ACE) Software plug-in available for device configuration, data capture, and performance evaluation ? Flexible analog front end ? On-board power solution and precision reference ? On-board clock gener

文件：3.41345 Mbytes 頁數(shù)：22 Pages

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32 μA, Ultra-Low Power, 16-Bit Sigma-Delta ADC with Integrated PGA and FIFO

FEATURES ? Ultra-low current consumption (typical) ? 32 μA: continuous conversion mode (gain = 128) ? 5 μA: duty cycling mode (ratio = 1/16) ? 0.5 μA: standby mode ? 0.1 μA: power-down mode ? Built-in features for system level power savings ? Current saving duty cycle ratio: 1/4 or 1/16 ?

文件：3.7831 Mbytes 頁數(shù)：107 Pages

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32 μA, Ultra Low Power, 16-Bit Sigma-Delta ADC with Integrated PGA and FIFO

FEATURES ? Ultra-low current consumption (typical): ? 32 μA: continuous conversion mode (gain = 128) ? 5 μA: duty cycling mode (ratio = 1/16) ? 0.5 μA: standby mode ? 0.1 μA: power-down mode ? Built-in features for system level power savings: ? Current saving duty cycle ratio: 1/4 or 1/16

文件：3.48095 Mbytes 頁數(shù)：105 Pages

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32 μA, Ultra-Low Power, 24-Bit Sigma-Delta ADC with Integrated PGA and FIFO

FEATURES ? Ultra-low current consumption (typical) ? 32 μA: continuous conversion mode (gain = 128) ? 5 μA: duty cycling mode (ratio = 1/16) ? 0.5 μA: standby mode ? 0.1 μA: power-down mode ? Built-in features for system level power savings ? Current saving duty cycle ratio: 1/4 or 1/16 ?

文件：3.89737 Mbytes 頁數(shù)：106 Pages

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32 關(guān)A, Ultra Low Power, 24-Bit Sigma-Delta ADC with Integrated PGA and FIFO

GENERAL DESCRIPTION The AD4130-8 is an ultra low power, high precision, measurement solution for low bandwidth battery operated applications. The fully integrated analog front end (AFE) includes a multiplexer for up to 16 single-ended or eight differential inputs, programmable gain amplifier

文件：3.54414 Mbytes 頁數(shù)：108 Pages

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32 μA, Ultra Low Power, 16-Bit Sigma-Delta ADC with Integrated PGA

FEATURES ? Ultra-low current consumption (typical): ? 32 μA: continuous conversion mode (gain = 128) ? 5 μA: duty cycling mode (ratio = 1/16) ? 0.5 μA: standby mode ? 0.1 μA: power-down mode ? Built-in features for system level power savings: ? Current saving duty cycle ratio: 1/4 or 1/16

文件：3.24212 Mbytes 頁數(shù)：94 Pages

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32 μA, Ultra-Low Power, 16-Bit Sigma-Delta ADC with Integrated PGA

FEATURES ? Ultra-low current consumption (typical) ? 32 μA: continuous conversion mode (gain = 128) ? 5 μA: duty cycling mode (ratio = 1/16) ? 0.5 μA: standby mode ? 0.1 μA: power-down mode ? Built-in features for system level power savings ? Current saving duty cycle ratio: 1/4 or 1/16 ?

文件：3.14233 Mbytes 頁數(shù)：94 Pages

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24-Bit, 62.5kSPS, Multichannel, Low-Noise Precision Sigma-Delta ADC

FEATURES ? Input referred noise: 10nV at 3.8SPS, Gain = 128 ? Crosspoint multiplexed analog inputs ? 4 Differential/8 Pseudodifferential inputs ? Ultra-low noise integrated PGA, gains of 0.5 to 128 ? Output data rate: 3.8SPS to 62.5kSPS ? Flexible digital filters ? Low latency sinc filters

文件：2.84789 Mbytes 頁數(shù)：94 Pages

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24-Bit, 62.5kSPS, Multichannel, Low-Noise Precision Sigma-Delta ADC

FEATURES ? Input referred noise: 10nV at 3.8SPS, Gain = 128 ? Crosspoint multiplexed analog inputs ? 4 Differential/8 Pseudodifferential inputs ? Ultra-low noise integrated PGA, gains of 0.5 to 128 ? Output data rate: 3.8SPS to 62.5kSPS ? Flexible digital filters ? Low latency sinc filters

文件：2.84846 Mbytes 頁數(shù)：94 Pages

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