3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

文件：958.34 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

文件：1.2766 Mbytes 頁數(shù)：18 Pages

TI

德州儀器

3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

文件：1.2766 Mbytes 頁數(shù)：18 Pages

TI

德州儀器

3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link??5 MHz

文件：217.69 Kbytes 頁數(shù)：9 Pages

NSC

國半

3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link??5 MHz

文件：262.55 Kbytes 頁數(shù)：11 Pages

TI

德州儀器

3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link??5 MHz

文件：262.55 Kbytes 頁數(shù)：11 Pages

TI

德州儀器

3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link??5 MHz

文件：262.55 Kbytes 頁數(shù)：11 Pages

TI

德州儀器

3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link??5 MHz

文件：262.55 Kbytes 頁數(shù)：11 Pages

TI

德州儀器

3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link??5 MHz

文件：262.55 Kbytes 頁數(shù)：11 Pages

TI

德州儀器

+3.3V LVDS 發(fā)送器 24 位平板顯示器 (FPD) 鏈路 - 65MHz

The DS90CF383B transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled an ? No Special Start-up Sequence Required Between Clock/Data and /PD Pins. Input Signal (Clock and Data) Can be Applied Either Before or After the Device is Powered.\n? Support Spread Spectrum Clocking Up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or ?5% Down Spread.\n?;

TI

德州儀器