DS90CF383B中文資料+3.3V LVDS 發(fā)送器 24 位平板顯示器 (FPD) 鏈路 - 65MHz數(shù)據(jù)手冊(cè)TI規(guī)格書

描述 Description

The DS90CF383B transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 227 Mbytes/sec. The DS90CF383B is fixed as a Falling edge strobe transmitter and will interoperate with a Falling edge strobe Receiver (DS90CF386) without any translation logic. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

特性 Features

? No Special Start-up Sequence Required Between Clock/Data and /PD Pins. Input Signal (Clock and Data) Can be Applied Either Before or After the Device is Powered.
? Support Spread Spectrum Clocking Up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or ?5% Down Spread.
? \"Input Clock Detection\" Feature Will Pull All LVDS Pairs to Logic Low when Input Clock is Missing and When /PD Pin is Logic High.
? 18 to 68 MHz Shift Clock Support
? Best–in–Class Set & Hold Times on TxINPUTs
? Tx Power Consumption

簡(jiǎn)介

DS90CF383B屬于集成電路（IC）的專用。由TI制造生產(chǎn)的DS90CF383B專用該系列產(chǎn)品可提供所需的功能，用以將信息源/信宿連到各種復(fù)雜或范圍狹窄應(yīng)用中的傳感器、變送器、致動(dòng)器、傳輸介質(zhì)或其他此類端點(diǎn)。例如，汽車安全氣囊驅(qū)動(dòng)器、車身控制和信息娛樂總線、自適應(yīng)電纜均衡器、智能卡等等。