T1/CEPT Jitter Attenuator

DESCRIPTION The DS2188 T1/CEPT Jitter Attenuator Chip contains a 128 X 2-bit buffer which, in conjunction with an external 4X crystal, is used to attenuate the incoming jitter present in clock and data. The device meets all of the latest applicable specifications including those outlined in TR 62

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DALLAS

T1/CEPT抖動抑制器

The DS2188 T1/CEPT jitter attenuator chip contains a 128 x 2-bit buffer that, in conjunction with an external 4X crystal, is used to attenuate the incoming jitter present in clock and data. The device meets all of the latest applicable specifications including those outlined in TR62411 (Accunet T1.5 \n? Attenuates clock and data jitter present in T1 or CEPT lines \n? Meets the jitter attenuation templates outlined in TR62411, TR-TSY-000170, G.735, and G.742 \n? Only one external component required; either a 6.176MHz (T1) or 8.192MHz (CEPT) crystal \n? Selectable buffer size of 128 bits or 32 bi;

ADI

亞德諾

Package：16-SOIC（0.295"，7.50mm 寬）；包裝：托盤 類別：集成電路（IC） 專用 IC 描述：IC JITTER ATTENUATOR 16SOIC

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亞德諾

Package：16-SOIC（0.295"，7.50mm 寬）；包裝：托盤 類別：集成電路（IC） 專用 IC 描述：IC JITTER ATTENUATOR 16SOIC

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亞德諾