3-STATE Dual 1-of-4 Line Data Selector/Multiplexer

General Description This Data Selector/Multiplexer contains full on-chip decoding to select one-of-four data sources as a result of a unique two-bit binary code at the Select Inputs. Each of the two Data Selector/Multiplexer circuits have their own separate Data and Output Control inputs and a no

文件：54.24 Kbytes 頁(yè)數(shù)：5 Pages

FAIRCHILD

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3-STATE Quad 1-of-2-Line Data Selector/Multiplexer

General Description These data selectors/multiplexers contain inverters and drivers to supply full on-chip data selection to the four 3-STATE outputs that can interface directly with data lines of bus-organized systems. A 4-bit word selected from one of two sources is routed to the four outputs.

文件：74.37 Kbytes 頁(yè)數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

3-STATE Quad 1-of-2-Line Data Selector/Multiplexer

General Description These data selectors/multiplexers contain inverters and drivers to supply full on-chip data selection to the four 3-STATE outputs that can interface directly with data lines of bus-organized systems. A 4-bit word selected from one of two sources is routed to the four outputs.

文件：74.37 Kbytes 頁(yè)數(shù)：7 Pages

FAIRCHILD

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3-STATE Quad 1-of-2-Line Data Selector/Multiplexer

General Description These data selectors/multiplexers contain inverters and drivers to supply full on-chip data selection to the four 3-STATE outputs that can interface directly with data lines of bus-organized systems. A 4-bit word selected from one of two sources is routed to the four outputs.

文件：74.37 Kbytes 頁(yè)數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

3-STATE Quad 1-of-2-Line Data Selector/Multiplexer

General Description These data selectors/multiplexers contain inverters and drivers to supply full on-chip data selection to the four 3-STATE outputs that can interface directly with data lines of bus-organized systems. A 4-bit word selected from one of two sources is routed to the four outputs.

文件：74.37 Kbytes 頁(yè)數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

3-STATE Quad 1-of-2-Line Data Selector/Multiplexer

General Description These data selectors/multiplexers contain inverters and drivers to supply full on-chip data selection to the four 3-STATE outputs that can interface directly with data lines of bus-organized systems. A 4-bit word selected from one of two sources is routed to the four outputs.

文件：74.37 Kbytes 頁(yè)數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

3-STATE Quad 1-of-2-Line Data Selector/Multiplexer

General Description These data selectors/multiplexers contain inverters and drivers to supply full on-chip data selection to the four 3-STATE outputs that can interface directly with data lines of bus-organized systems. A 4-bit word selected from one of two sources is routed to the four outputs.

文件：74.37 Kbytes 頁(yè)數(shù)：7 Pages

FAIRCHILD

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Triple 3-Input NOR Gate

General Description This device contains three independent gates, each of which performs the logic NOR function. Features ■Switching specifications at 50 pF ■Switching specifications guaranteed over full temperature and VCCrange ■Advanced oxide-isolated, ion-implanted Schottky TTL

文件：46.43 Kbytes 頁(yè)數(shù)：4 Pages

FAIRCHILD

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Octal D-Type Edge-Triggered Flip-Flop with Clear

General Description These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup requirements is transferred to the Q outputs on the positive-going edge of the clock pulse.

文件：183.6 Kbytes 頁(yè)數(shù)：9 Pages

ONSEMI

安森美半導(dǎo)體

Octal D-Type Edge-Triggered Flip-Flop with Clear

General Description These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup requirements is transferred to the Q outputs on the positive-going edge of the clock pul

文件：76.76 Kbytes 頁(yè)數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體