3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：144.4 Kbytes 頁數(shù)：11 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：534.29 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

適用于 DRAM 應用且具有 9 個輸出的 3.3V 鎖相環(huán)路時鐘驅動器

The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2509 operate ? Use CDCVF2509A (SCAS765) as a Replacement for This Device\n? Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1\n? Spread Spectrum Clock Compatible\n? Operating Frequency 50 MHz to 175 MHz\n? Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps\n? Jitter (cyc;

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：534.29 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：537.61 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：164.97 Kbytes 頁數(shù)：12 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：537.61 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：164.97 Kbytes 頁數(shù)：12 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：537.61 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：537.61 Kbytes 頁數(shù)：18 Pages

TI

德州儀器