3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：164.97 Kbytes 頁數(shù)：12 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：537.61 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：537.61 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：537.61 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：164.97 Kbytes 頁數(shù)：12 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：537.61 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：537.61 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：164.97 Kbytes 頁數(shù)：12 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：537.61 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

具有斷電模式的 3.3V 鎖相環(huán)路時鐘驅(qū)動器

The CDCVF2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2509A opera ? Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1\n? Operating Frequency 20 MHz to 175 MHz\n? Jitter (cyc - cyc) at 60 MHz to 175 MHz Is Typ = 65 ps\n? Auto Frequency Detection to Disable Device (Power-Down Mode)\n? Phase-Lock Loop Clock Distribution for Synchronous D;

TI

德州儀器