CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features ? Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required ? Supply voltage: 3 V to 3.6 V ? Operating frequency: 8 MHz to 200 MHz ? Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz ? Power-down mode avai

文件：1.18376 Mbytes 頁數(shù)：26 Pages

TI

德州儀器

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：161.19 Kbytes 頁數(shù)：12 Pages

TI

德州儀器

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

文件：596.43 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

1:8 3.3V 鎖相環(huán)路時鐘驅(qū)動器

The CDCVF25081 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks to the input clock signal. The CDCVF25081 operates from a nominal supply voltage of 3.3 V. The device also includes integrated se ? Phase-Locked Loop-Based Zero-Delay Buffer\n? Operating Frequency: 10 MHz to 200 MHz\n? Low Jitter (Cycle-Cycle): ±100 ps Over the Range 66 MHz to 200 MHz\n? Distributes One Clock Input to Two Banks of Four Outputs\n? Auto Frequency Detection to Disable Device (Power Down Mode)\n? Consumes Less Tha;

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/ckv25081/marking.html">CKV25081；Package：SOIC；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features ? Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required ? Supply voltage: 3 V to 3.6 V ? Operating frequency: 8 MHz to 200 MHz ? Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz ? Power-down mode avai

文件：1.18376 Mbytes 頁數(shù)：26 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/ckv25081/marking.html">CKV25081；Package：SOIC；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features ? Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required ? Supply voltage: 3 V to 3.6 V ? Operating frequency: 8 MHz to 200 MHz ? Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz ? Power-down mode avai

文件：1.18376 Mbytes 頁數(shù)：26 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/ck081/marking.html">CK081；Package：TSSOP；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features ? Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required ? Supply voltage: 3 V to 3.6 V ? Operating frequency: 8 MHz to 200 MHz ? Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz ? Power-down mode avai

文件：1.18376 Mbytes 頁數(shù)：26 Pages

TI

德州儀器

絲印：CK081；Package：TSSOP；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features ? Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required ? Supply voltage: 3 V to 3.6 V ? Operating frequency: 8 MHz to 200 MHz ? Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz ? Power-down mode avai

文件：1.18376 Mbytes 頁數(shù)：26 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/ck081/marking.html">CK081；Package：TSSOP；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features ? Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required ? Supply voltage: 3 V to 3.6 V ? Operating frequency: 8 MHz to 200 MHz ? Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz ? Power-down mode avai

文件：1.18376 Mbytes 頁數(shù)：26 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/ck081/marking.html">CK081；Package：TSSOP；CDCVF25081 3.3-V Phased-Lock Loop Clock Driver

1 Features ? Phase-locked loop based, zero-delay buffer – 1 clock input to 2 banks of 4 outputs – No external RC network required ? Supply voltage: 3 V to 3.6 V ? Operating frequency: 8 MHz to 200 MHz ? Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz ? Power-down mode avai

文件：1.18376 Mbytes 頁數(shù)：26 Pages

TI

德州儀器