3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER

文件：549.51 Kbytes 頁數(shù)：14 Pages

TI

德州儀器

3.3-V Clock Phase-Lock Loop Clock Driver

文件：1.19077 Mbytes 頁數(shù)：23 Pages

TI

德州儀器

3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER

文件：549.51 Kbytes 頁數(shù)：14 Pages

TI

德州儀器

3.3-V Clock Phase-Lock Loop Clock Driver

文件：1.19077 Mbytes 頁數(shù)：23 Pages

TI

德州儀器

3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER

文件：369.62 Kbytes 頁數(shù)：14 Pages

TI

德州儀器

3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER

文件：369.62 Kbytes 頁數(shù)：14 Pages

TI

德州儀器

3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER

文件：549.51 Kbytes 頁數(shù)：14 Pages

TI

德州儀器

3.3-V Clock Phase-Lock Loop Clock Driver

文件：1.19077 Mbytes 頁數(shù)：23 Pages

TI

德州儀器

3.3-V CLOCK PHASE-LOCKED LOOP CLOCK DRIVER

文件：225.62 Kbytes 頁數(shù)：10 Pages

TI

德州儀器

適用于兼容擴(kuò)展頻譜的同步、DRAM 和通用應(yīng)用的汽車 PLL 時(shí)鐘驅(qū)動(dòng)器

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0?3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series- ? Qualified for Automotive Applications\n? Phase-Locked Loop Clock Driver for Synchronous DRAM and General-Purpose Applications\n? Spread-Spectrum Clock Compatible\n? Operating Frequency: 24 MHz to 200 MHz\n? Low Jitter (Cycle-to-Cycle): Range 66 MHz to 200 MHz\n? Distributes One Clock Input to One ;

TI

德州儀器