CDCM1802 Clock Buffer With Programmable Divider, LVPECL I/O Additional LVCMOS Output

1 Features 1? Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output ? Programmable Output Divider for Both LVPECL and LVCMOS Outputs ? 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise ? 3.3-V Power Suppl

文件：1.15535 Mbytes 頁(yè)數(shù)：30 Pages

TI

德州儀器

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O ADDITIONAL LVCMOS OUTPUT

文件：695.86 Kbytes 頁(yè)數(shù)：22 Pages

TI

德州儀器

CDCM1802 Clock Buffer With Programmable Divider, LVPECL I/O Additional LVCMOS Output

文件：1.42326 Mbytes 頁(yè)數(shù)：30 Pages

TI

德州儀器

具有可編程分頻器的時(shí)鐘緩沖器，LVPECL I/O 和 LVCMOS 輸出

The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair, Y0 and Y0, and one single-ended LVCMOS output, Y1. It is specifically designed for driving 50-Ω transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output sta ? Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output\n? 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise\n? Signaling Rate Up to 800-MHz LVPECL and 200-MHz LVCMOS\n? Receiver Input Threshold ±75 mV\n? 16-Pin V;

TI

德州儀器

絲印：AJW；Package：VQFN；CDCM1802 Clock Buffer With Programmable Divider, LVPECL I/O Additional LVCMOS Output

1 Features 1? Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output ? Programmable Output Divider for Both LVPECL and LVCMOS Outputs ? 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise ? 3.3-V Power Suppl

文件：1.15535 Mbytes 頁(yè)數(shù)：30 Pages

TI

德州儀器

絲印：AJW；Package：VQFN；CDCM1802 Clock Buffer With Programmable Divider, LVPECL I/O Additional LVCMOS Output

1 Features 1? Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output ? Programmable Output Divider for Both LVPECL and LVCMOS Outputs ? 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise ? 3.3-V Power Suppl

文件：1.15535 Mbytes 頁(yè)數(shù)：30 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/ajw/marking.html">AJW；Package：VQFN；CDCM1802 Clock Buffer With Programmable Divider, LVPECL I/O Additional LVCMOS Output

1 Features 1? Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output ? Programmable Output Divider for Both LVPECL and LVCMOS Outputs ? 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise ? 3.3-V Power Suppl

文件：1.15535 Mbytes 頁(yè)數(shù)：30 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/ajw/marking.html">AJW；Package：VQFN；CDCM1802 Clock Buffer With Programmable Divider, LVPECL I/O Additional LVCMOS Output

1 Features 1? Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output ? Programmable Output Divider for Both LVPECL and LVCMOS Outputs ? 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise ? 3.3-V Power Suppl

文件：1.15535 Mbytes 頁(yè)數(shù)：30 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/ajw/marking.html">AJW；Package：VQFN；CDCM1802 Clock Buffer With Programmable Divider, LVPECL I/O Additional LVCMOS Output

1 Features 1? Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output ? Programmable Output Divider for Both LVPECL and LVCMOS Outputs ? 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise ? 3.3-V Power Suppl

文件：1.15535 Mbytes 頁(yè)數(shù)：30 Pages

TI

德州儀器

CDCM1802 Clock Buffer With Programmable Divider, LVPECL I/O Additional LVCMOS Output

文件：1.42326 Mbytes 頁(yè)數(shù)：30 Pages

TI

德州儀器