絲?。?a target="_blank" title="Marking" href="/cdc706/marking.html">CDC706；Package：TSSOP；PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER

1FEATURES 2? High Performance 3:6 PLL Based Clock Synthesizer / Multiplier / Divider ? User Programmable PLL Frequencies ? Easy In-Circuit Programming via SMBus Data Interface ? Wide PLL Divider Ratio Allows 0-PPM Output Clock Error ? Clock Inputs Accept a Crystal or a Single-Ended LVCMOS

文件：1.21503 Mbytes 頁(yè)數(shù)：44 Pages

TI

德州儀器

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER

文件：1.64453 Mbytes 頁(yè)數(shù)：32 Pages

TI

德州儀器

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER

文件：1.030829 Mbytes 頁(yè)數(shù)：40 Pages

TI

德州儀器

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER

1FEATURES · High-Performance 3:6 PLL-Based Clock Synthesizer/Multiplier/Divider · User-Programmable PLL Frequencies · EEPROM Programming Without the Need to Apply High Programming Voltage · Easy In-Circuit Programming via SMBus Data Interface · Wide PLL Divider Ratio Allows 0-ppm Output C

文件：1.22229 Mbytes 頁(yè)數(shù)：46 Pages

TI

德州儀器