3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2510A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to Four Banks of Four Outputs Separate Output Enable for Each Output Bank External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the

文件：569.86 Kbytes 頁數：18 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：160.08 Kbytes 頁數：11 Pages

TI

德州儀器

絲?。?strong>CDC516；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2510A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to Four Banks of Four Outputs Separate Output Enable for Each Output Bank External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the

文件：569.86 Kbytes 頁數：18 Pages

TI

德州儀器

絲?。?strong>CDC516；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2510A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to Four Banks of Four Outputs Separate Output Enable for Each Output Bank External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the

文件：569.86 Kbytes 頁數：18 Pages

TI

德州儀器

絲?。?strong>CDC516；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2510A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to Four Banks of Four Outputs Separate Output Enable for Each Output Bank External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the

文件：569.86 Kbytes 頁數：18 Pages

TI

德州儀器

絲?。?strong>CDC516；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2510A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to Four Banks of Four Outputs Separate Output Enable for Each Output Bank External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the

文件：569.86 Kbytes 頁數：18 Pages

TI

德州儀器

絲?。?strong>CDC516；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2510A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to Four Banks of Four Outputs Separate Output Enable for Each Output Bank External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the

文件：569.86 Kbytes 頁數：18 Pages

TI

德州儀器

具有三態(tài)輸出的 3.3V 相位鎖定環(huán)路時鐘驅動器

The CDC516 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback output (FBOUT) to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC516 o ? Use CDCVF2510A as a Replacement for this Device\n? Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications\n? Distributes One Clock Input to Four Banks of Four Outputs\n? Separate Output Enable for Each Output Bank\n? External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to ;

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：160.08 Kbytes 頁數：11 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：160.08 Kbytes 頁數：11 Pages

TI

德州儀器