CDx4HCT10 Triple 3-Input NAND Gates

1 Features ? LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V ? CMOS input logic compatible – II ≤ 1 μA at VOL, VOH ? Buffered inputs ? 4.5 V to 5.5 V operation ? Wide operating temperature range: -55°C to +125°C ? Supports fanout up to 10 LSTTL loads ? Significant power r

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德州儀器

High Speed CMOS Logic Triple 3-Input NAND Gate

文件：41.15 Kbytes 頁數(shù)：6 Pages

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德州儀器

High-Speed CMOS Logic Triple 3-Input NAND Gate

文件：265.51 Kbytes 頁數(shù)：10 Pages

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德州儀器

High-Speed CMOS Logic Triple 3-Input NAND Gate

文件：261.209 Kbytes 頁數(shù)：11 Pages

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德州儀器

High-Speed CMOS Logic Triple 3-Input NAND Gate

文件：32.159 Kbytes 頁數(shù)：5 Pages

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德州儀器

High-Speed CMOS Logic Triple 3-Input NAND Gate

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德州儀器

具有 TTL 兼容型 CMOS 輸入的 3 通道、3 輸入、4.5V 至 5.5V 與非門

This device contains three independent 3-input NAND gates. Each gate performs the Boolean function Y?=? A?●?B?●?C in positive logic. ? LSTTL input logic compatible \n? CMOS input logic compatible \n? Buffered inputs\n? Wide operating temperature range: -55°C?to?+125°C\n? Significant power reduction compared to LSTTL logic ICs;

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德州儀器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features ? Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times ? Asynchronous Reset ? Complementary Outputs ? Buffered Inputs ? Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC ? Fanout (Over Temperature Range) - Standard Outputs . . . . .

文件：609.54 Kbytes 頁數(shù)：20 Pages

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德州儀器

絲?。?a target="_blank" title="Marking" href="/cd74hct107e/marking.html">CD74HCT107E；Package：PDIP；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features ? Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times ? Asynchronous Reset ? Complementary Outputs ? Buffered Inputs ? Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC ? Fanout (Over Temperature Range) - Standard Outputs . . . . .

文件：609.54 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd74hct107e/marking.html">CD74HCT107E；Package：PDIP；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features ? Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times ? Asynchronous Reset ? Complementary Outputs ? Buffered Inputs ? Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC ? Fanout (Over Temperature Range) - Standard Outputs . . . . .

文件：609.54 Kbytes 頁數(shù)：20 Pages

TI

德州儀器