絲?。?a target="_blank" title="Marking" href="/cd74hct107e/marking.html">CD74HCT107E；Package：PDIP；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features ? Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times ? Asynchronous Reset ? Complementary Outputs ? Buffered Inputs ? Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC ? Fanout (Over Temperature Range) - Standard Outputs . . . . .

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TI

德州儀器

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

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PHI

PHI

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J

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NEXPERIA

安世

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

文件：53.67 Kbytes 頁數(shù)：7 Pages

PHI

PHI