絲印：CD54AC109F3A；Package：CDIP；CDx4AC109 Dual J-K Positive-Edge-Triggered Flip-flops with Clear and Preset

1 Features ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage ? Speed of bipolar F, AS, and S, with significantly reduced power consumption ? Balanced propagation delays ? ±24mA output drive current – Fanout to 15 F devices ? SCR-latchup

文件：1.09024 Mbytes 頁數(shù)：22 Pages

TI

德州儀器

Dual “J-K” Flip-Flop with Set and Reset

Description The CD54AC112/3A and CD54ACT112/3A are dual “J-K” flip-flops with set and reset that utilize the Harris Advanced CMOS Logic technology. The CD54AC112/3A and CD54ACT112/3A are supplied in 16 lead dual-in-line ceramic packages (F suffix).

文件：10.3 Kbytes 頁數(shù)：1 Pages

INTERSIL

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Pro

文件：426.59 Kbytes 頁數(shù)：15 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd54ac112f3a/marking.html">CD54AC112F3A；Package：CDIP；DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Pro

文件：426.59 Kbytes 頁數(shù)：15 Pages

TI

德州儀器

絲印：CD54AC112F3A；Package：CDIP；DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Pro

文件：426.59 Kbytes 頁數(shù)：15 Pages

TI

德州儀器

Dual “J-K” Flip-Flop with Set and Reset

Description The CD54AC112/3A and CD54ACT112/3A are dual “J-K” flip-flops with set and reset that utilize the Harris Advanced CMOS Logic technology. The CD54AC112/3A and CD54ACT112/3A are supplied in 16 lead dual-in-line ceramic packages (F suffix).

文件：10.3 Kbytes 頁數(shù)：1 Pages

INTERSIL

CDx4AC138 3-Line to 8-Line Decoders/Demultiplexers

1 Features ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30 of the supply voltage ? Speed of bipolar F, AS, and S, with significantly reduced power consumption ? Designed specifically for high-speed memory decoders and data-transmission systems ? Incorporate thre

文件：2.44568 Mbytes 頁數(shù)：30 Pages

TI

德州儀器

CDx4AC138 3-Line to 8-Line Decoders/Demultiplexers

1 Features ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30 of the supply voltage ? Speed of bipolar F, AS, and S, with significantly reduced power consumption ? Designed specifically for high-speed memory decoders and data-transmission systems ? Incorporate thre

文件：2.44568 Mbytes 頁數(shù)：30 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd54ac138f3a/marking.html">CD54AC138F3A；Package：CDIP；CDx4AC138 3-Line to 8-Line Decoders/Demultiplexers

1 Features ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30 of the supply voltage ? Speed of bipolar F, AS, and S, with significantly reduced power consumption ? Designed specifically for high-speed memory decoders and data-transmission systems ? Incorporate thre

文件：2.44568 Mbytes 頁數(shù)：30 Pages

TI

德州儀器

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Buffered Inputs Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation

文件：413.25 Kbytes 頁數(shù)：14 Pages

TI

德州儀器