| 型號(hào) | 下載 訂購(gòu) | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
CDx4AC08 Quadruple 2-Input Positive-and Gates 1 Features ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage ? Speed of bipolar F, AS, and S, with significantly reduced power consumption ? Balanced propagation delays ? Buffered inputs ? ±24mA output drive current - Fanout to 15 F dev 文件:1.2263 Mbytes 頁(yè)數(shù):23 Pages | TI 德州儀器 | TI | ||
絲印:CD54AC08F3A;Package:CDIP;CDx4AC08 Quadruple 2-Input Positive-and Gates 1 Features ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage ? Speed of bipolar F, AS, and S, with significantly reduced power consumption ? Balanced propagation delays ? Buffered inputs ? ±24mA output drive current - Fanout to 15 F dev 文件:1.2263 Mbytes 頁(yè)數(shù):23 Pages | TI 德州儀器 | TI | ||
絲印:CD54AC08F3A;Package:CDIP;CDx4AC08 Quadruple 2-Input Positive-and Gates 1 Features ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage ? Speed of bipolar F, AS, and S, with significantly reduced power consumption ? Balanced propagation delays ? Buffered inputs ? ±24mA output drive current - Fanout to 15 F dev 文件:1.2263 Mbytes 頁(yè)數(shù):23 Pages | TI 德州儀器 | TI | ||
Dual J-K Flip-Flop with Set and Reset Description The CD54AC109/3A and CD54ACT109/3A are dual “J-K” flip-flops with set and reset that utilize the Harris Advanced CMOS Logic technology. These flip-flops have independent J, K, Set, Reset and Clock inputs and Q and Q outputs. The CD54AC109/3A and CD54ACT109/3A changes state on the posi 文件:10.39 Kbytes 頁(yè)數(shù):1 Pages | INTERSIL | INTERSIL | ||
Dual J-K Flip-Flop with Set and Reset Description The CD54AC109/3A and CD54ACT109/3A are dual “J-K” flip-flops with set and reset that utilize the Harris Advanced CMOS Logic technology. These flip-flops have independent J, K, Set, Reset and Clock inputs and Q and Q outputs. The CD54AC109/3A and CD54ACT109/3A changes state on the posi 文件:10.39 Kbytes 頁(yè)數(shù):1 Pages | INTERSIL | INTERSIL | ||
CDx4AC109 Dual J-K Positive-Edge-Triggered Flip-flops with Clear and Preset 1 Features ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage ? Speed of bipolar F, AS, and S, with significantly reduced power consumption ? Balanced propagation delays ? ±24mA output drive current – Fanout to 15 F devices ? SCR-latchup 文件:1.09024 Mbytes 頁(yè)數(shù):22 Pages | TI 德州儀器 | TI | ||
絲印:CD54AC109F3A;Package:CDIP;CDx4AC109 Dual J-K Positive-Edge-Triggered Flip-flops with Clear and Preset 1 Features ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage ? Speed of bipolar F, AS, and S, with significantly reduced power consumption ? Balanced propagation delays ? ±24mA output drive current – Fanout to 15 F devices ? SCR-latchup 文件:1.09024 Mbytes 頁(yè)數(shù):22 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/cd54ac109f3a/marking.html">CD54AC109F3A;Package:CDIP;CDx4AC109 Dual J-K Positive-Edge-Triggered Flip-flops with Clear and Preset 1 Features ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage ? Speed of bipolar F, AS, and S, with significantly reduced power consumption ? Balanced propagation delays ? ±24mA output drive current – Fanout to 15 F devices ? SCR-latchup 文件:1.09024 Mbytes 頁(yè)數(shù):22 Pages | TI 德州儀器 | TI | ||
Dual “J-K” Flip-Flop with Set and Reset Description The CD54AC112/3A and CD54ACT112/3A are dual “J-K” flip-flops with set and reset that utilize the Harris Advanced CMOS Logic technology. The CD54AC112/3A and CD54ACT112/3A are supplied in 16 lead dual-in-line ceramic packages (F suffix). 文件:10.3 Kbytes 頁(yè)數(shù):1 Pages | INTERSIL | INTERSIL | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Pro 文件:426.59 Kbytes 頁(yè)數(shù):15 Pages | TI 德州儀器 | TI |
替換型號(hào)
晶體管資料
- 型號(hào):
- 別名:
三極管、晶體管、晶體三極管
- 生產(chǎn)廠家:
- 制作材料:
Si-NPN
- 性質(zhì):
調(diào)頻 (FM)_前置放大 (V)_混頻 (M)
- 封裝形式:
直插封裝
- 極限工作電壓:
- 最大電流允許值:
- 最大工作頻率:
200MHZ
- 引腳數(shù):
3
- 可代換的型號(hào):
BF255,
- 最大耗散功率:
- 放大倍數(shù):
- 圖片代號(hào):
C-78
- vtest:
0
- htest:
200000000
- atest:
0
- wtest:
0
技術(shù)參數(shù)
- 范圍:
24Vdc
- 功率:
92W
- 輸入:
DC 24V
- 尺寸寬x高x深(mm):
102
- 特殊特性:
NEC Class 2
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
HAR |
24+ |
5650 |
公司原廠原裝現(xiàn)貨假一罰十!特價(jià)出售!強(qiáng)勢(shì)庫(kù)存! |
詢(xún)價(jià) | |||
PULS, LP |
2010+ |
N/A |
95 |
加我qq或微信,了解更多詳細(xì)信息,體驗(yàn)一站式購(gòu)物 |
詢(xún)價(jià) | ||
TI/德州儀器 |
23+ |
DIP-14 |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢(xún)價(jià) | ||
TI(德州儀器) |
23+ |
- |
13650 |
公司只做原裝正品,假一賠十 |
詢(xún)價(jià) | ||
TI/德州儀器 |
CDIP20 |
23+ |
6000 |
原裝現(xiàn)貨有上庫(kù)存就有貨全網(wǎng)最低假一賠萬(wàn) |
詢(xún)價(jià) | ||
TI |
1907 |
327 |
全新原裝現(xiàn)貨 |
詢(xún)價(jià) | |||
SUMIDA |
2022+ |
SMD |
30000 |
原廠代理 終端免費(fèi)提供樣品 |
詢(xún)價(jià) | ||
TI |
22+ |
DIP |
2000 |
原裝現(xiàn)貨庫(kù)存.價(jià)格優(yōu)勢(shì)!! |
詢(xún)價(jià) | ||
TI |
24+ |
DIP |
48650 |
原裝正品 特價(jià)現(xiàn)貨(香港 新加坡 日本) |
詢(xún)價(jià) | ||
TI/德州儀器 |
25+ |
CDIP |
16 |
就找我吧!--邀您體驗(yàn)愉快問(wèn)購(gòu)元件! |
詢(xún)價(jià) |
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