CMOS DUAL 4-BIT LATCH

文件：228.36 Kbytes 頁(yè)數(shù)：14 Pages

TI

德州儀器

Cmos Dual 4-Bit Latch

文件：1.02825 Mbytes 頁(yè)數(shù)：15 Pages

TI

德州儀器

CMOS DUAL 4-BIT LATCH

文件：228.36 Kbytes 頁(yè)數(shù)：14 Pages

TI

德州儀器

CMOS 雙路 4 位鎖存器

CD4508B dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE control. With the STROBE line in the high state, the data on the \"D\" inputs appear at the corresponding \"Q\" outputs provided the DISABLE line is in the low state. Changing the STROBE lin ? Two independent 4-bit latches\n? 3-state outputs with high-impedance state for bus line applications\n? 100% tested for quiescent current at 20 V\n? Standardized, symmetrical output characteristics\n? Noise margin (full package-temperature range) = ????????1 V at VDD = 5 V ????????2 V at VDD =;

TI

德州儀器

CMOS 雙路 4 位鎖存器

CD4508B dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE control. With the STROBE line in the high state, the data on the \"D\" inputs appear at the corresponding \"Q\" outputs provided the DISABLE line is in the low state. Changing the STROBE lin ? Two independent 4-bit latches\n? 3-state outputs with high-impedance state for bus line applications\n? 100% tested for quiescent current at 20 V\n? Standardized, symmetrical output characteristics\n? Noise margin (full package-temperature range) = ????????1 V at VDD = 5 V ????????2 V at VDD =;

TI

德州儀器

CMOS Dual 4-Bit Latch

Renesas

瑞薩

Package：24-DIP（0.600"，15.24mm）；包裝：卷帶（TR） 類別：集成電路（IC） 鎖存器 描述：IC DUAL 4BIT LATCH 20V 24-DIP

TI

德州儀器

Package：24-SOIC（0.295"，7.50mm 寬）；包裝：管件 類別：集成電路（IC） 鎖存器 描述：IC DUAL 4BIT LATCH 20V 24-SOIC

TI

德州儀器

Package：24-SOIC（0.295"，7.50mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 鎖存器 描述：IC DUAL 4BIT LATCH 20V 24SOIC

TI

德州儀器