| 型號(hào) | 下載 訂購(gòu) | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
絲印:CD4508BM;Package:SOIC;CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件:650.82 Kbytes 頁(yè)數(shù):17 Pages | TI 德州儀器 | TI | ||
絲印:CD4508BM;Package:SOIC;CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件:650.82 Kbytes 頁(yè)數(shù):17 Pages | TI 德州儀器 | TI | ||
CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件:650.82 Kbytes 頁(yè)數(shù):17 Pages | TI 德州儀器 | TI | ||
CMOS Dual 4-Bit Latch Description CD4508BMS dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE controls. With the STROBE line in the high state, the data on the D inputs appear at the corresponding Q outputs provided the DISABLE line is in the low state. Changing the 文件:85.96 Kbytes 頁(yè)數(shù):9 Pages | INTERSIL | INTERSIL | ||
絲?。?a target="_blank" title="Marking" href="/cm508b/marking.html">CM508B;Package:TSSOP;CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件:650.82 Kbytes 頁(yè)數(shù):17 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/cm508b/marking.html">CM508B;Package:TSSOP;CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件:650.82 Kbytes 頁(yè)數(shù):17 Pages | TI 德州儀器 | TI | ||
Cmos Dual 4-Bit Latch 文件:1.02825 Mbytes 頁(yè)數(shù):15 Pages | TI 德州儀器 | TI | ||
Cmos Dual 4-Bit Latch 文件:1.02825 Mbytes 頁(yè)數(shù):15 Pages | TI 德州儀器 | TI | ||
CMOS DUAL 4-BIT LATCH 文件:228.36 Kbytes 頁(yè)數(shù):14 Pages | TI 德州儀器 | TI | ||
CMOS DUAL 4-BIT LATCH 文件:228.36 Kbytes 頁(yè)數(shù):14 Pages | TI 德州儀器 | TI |
替換型號(hào)
技術(shù)參數(shù)
- Technology Family:
CD4000
- Supply voltage (Min) (V):
3
- Supply voltage (Max) (V):
18
- Input type:
Standard CMOS
- Output type:
3-State
- Clock Frequency (Max) (MHz):
8
- IOL (Max) (mA):
2.4
- IOH (Max) (mA):
-2.4
- ICC (Max) (uA):
3000
- Features:
Standard speed (tpd > 50ns)
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
TI |
00/01+ |
TSSOP-14 |
722 |
全新原裝100真實(shí)現(xiàn)貨供應(yīng) |
詢價(jià) | ||
TI |
25+ |
TSSOP-14 |
860 |
⊙⊙新加坡大量現(xiàn)貨庫(kù)存,深圳常備現(xiàn)貨!歡迎查詢!⊙ |
詢價(jià) | ||
TI |
24+ |
TSSOP-24 |
5650 |
公司原廠原裝現(xiàn)貨假一罰十!特價(jià)出售!強(qiáng)勢(shì)庫(kù)存! |
詢價(jià) | ||
TI德州儀器 |
22+ |
24000 |
原裝正品現(xiàn)貨,實(shí)單可談,量大價(jià)優(yōu) |
詢價(jià) | |||
HAR |
24+ |
1 |
詢價(jià) | ||||
H |
24+ |
CDIP24P |
6980 |
原裝現(xiàn)貨,可開(kāi)13%稅票 |
詢價(jià) | ||
HARRIS |
25+ |
DIP |
18000 |
原廠直接發(fā)貨進(jìn)口原裝 |
詢價(jià) | ||
TI |
23+ |
SOP-24 |
3200 |
絕對(duì)全新原裝!優(yōu)勢(shì)供貨渠道!特價(jià)!請(qǐng)放心訂購(gòu)! |
詢價(jià) | ||
TI |
2015+ |
DIP |
19889 |
一級(jí)代理原裝現(xiàn)貨,特價(jià)熱賣! |
詢價(jià) | ||
TI |
24+/25+ |
42 |
原裝正品現(xiàn)貨庫(kù)存價(jià)優(yōu) |
詢價(jià) |
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