8-Bit Shift Register/Latch with 3-STATE Outputs

General Description The CD4094BC consists of an 8-bit shift register and a 3-STATE 8-bit latch. Data is shifted serially through the shift register on the positive transition of the clock. The output of the last stage (QS) can be used to cascade several devices. Data on the QSoutput is transfer

文件：68.55 Kbytes 頁數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

絲印：CD4094BE；Package：PDIP；CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

文件：924.5 Kbytes 頁數(shù)：19 Pages

TI

德州儀器

絲印：CD4094BE；Package：PDIP；CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

文件：924.5 Kbytes 頁數(shù)：19 Pages

TI

德州儀器

絲印：CD4094BE；Package：PDIP；CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

文件：924.5 Kbytes 頁數(shù)：19 Pages

TI

德州儀器

絲印：CD4094BF；Package：CDIP；CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

文件：924.5 Kbytes 頁數(shù)：19 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd4094bf/marking.html">CD4094BF；Package：CDIP；CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

文件：924.5 Kbytes 頁數(shù)：19 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/7702501ea/marking.html">7702501EA；Package：CDIP；CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

文件：924.5 Kbytes 頁數(shù)：19 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/7702501ea/marking.html">7702501EA；Package：CDIP；CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

文件：924.5 Kbytes 頁數(shù)：19 Pages

TI

德州儀器

CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

文件：924.5 Kbytes 頁數(shù)：19 Pages

TI

德州儀器

CMOS 8-Stage Shift-and-Store Bus Register

Description CD4094BMS is a 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock trans

文件：87.8 Kbytes 頁數(shù)：11 Pages

INTERSIL