8-Bit Shift Register/Latch with 3-STATE Outputs

General Description The CD4094BC consists of an 8-bit shift register and a 3-STATE 8-bit latch. Data is shifted serially through the shift register on the positive transition of the clock. The output of the last stage (QS) can be used to cascade several devices. Data on the QSoutput is transfer

文件：68.55 Kbytes 頁(yè)數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

CMOS 8-Stage Shift-and-Store Bus Register

Description CD4094BMS is a 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock trans

文件：87.8 Kbytes 頁(yè)數(shù)：11 Pages

INTERSIL

CMOS 8-Stage Shift-and-Store Bus Register

Features ? High Voltage Type (20V Rating) ? 3-State Parallel Outputs for Connection to Common Bus ? Separate Serial Outputs Synchronous to Both Positive and Negative Clock Edges for Cascading ? Medium Speed Operation - 5MHz at 10V (typ) ? Standardized Symmetrical Output Characteristics ? 1

文件：130.889 Kbytes 頁(yè)數(shù)：11 Pages

SYC

CMOS 8-STAGE SHIFT-AND-STORE BUS REGISTER

文件：281.11 Kbytes 頁(yè)數(shù)：5 Pages

TI

德州儀器

8階移位鎖存總線寄存器

The CD4094 is an 8-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive-going clock trans ? Wide supply voltage range from 3V to 15V\n? Fully static operation\n? 5V, 10V, and 15V parametric ratings\n? Standardized symmetrical output characteristics\n? Specified from -40℃ to +125℃\n? Packaging information: DIP16/SOP16/TSSOP16;

I-CORE

中微愛(ài)芯

CMOS 8-STAGE SHIFT-AND-STORE BUS REGISTER

TI

德州儀器

8階移位鎖存總線寄存器，8-stage Shift-and-store Bus Register

CKS

中科芯

CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

文件：924.5 Kbytes 頁(yè)數(shù)：19 Pages

TI

德州儀器

8-Bit Shift Register/Latch with 3-STATE Outputs

General Description The CD4094BC consists of an 8-bit shift register and a 3-STATE 8-bit latch. Data is shifted serially through the shift register on the positive transition of the clock. The output of the last stage (QS) can be used to cascade several devices. Data on the QSoutput is transfer

文件：68.55 Kbytes 頁(yè)數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

8-Bit Shift Register/Latch with 3-STATE Outputs

General Description The CD4094BC consists of an 8-bit shift register and a 3-STATE 8-bit latch. Data is shifted serially through the shift register on the positive transition of the clock. The output of the last stage (QS) can be used to cascade several devices. Data on the QSoutput is transfer

文件：68.55 Kbytes 頁(yè)數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體