Hex Buffers (Non-Inverting)

General Description The CD4010C hex buffers are monolithic complementary MOS (CMOS) integrated circuits. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage. This results in high noise immunity over a wide su

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FAIRCHILD

仙童半導(dǎo)體

CMOS HEX BUFFERS/CONVERTERS

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TI

德州儀器

CMOS 32-Stage Static Left/Right Shift Register

Description CD40100BMS is a 32-Stage shift register containing 32 D-type master-slave flip-flops. The data present at the SHIFT RIGHT INPUT is transferred into the first register stage synchronously with the positive CLOCK edge, provided the LEFT/RIGHT CONTROL is at a low level, the RECIRCUL

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INTERSIL

CMOS 9-Bit Parity Generator/Checker

Description The CD40101BMS is a 9-bit (8 data bits plus 1 parity bit) parity generator/checker. It may be used to detect errors in data transmission or data retrieval. Odd and even outputs facilitate odd or even parity generation and checking. When used as a parity generator, a parity bit is

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INTERSIL

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

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TI

德州儀器

絲印：CD40102BE；Package：PDIP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 頁(yè)數(shù)：22 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd40102be/marking.html">CD40102BE；Package：PDIP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 頁(yè)數(shù)：22 Pages

TI

德州儀器

CMOS 8-Stage Presettable Synchronous Down Counters

Description CD40102BMS and CD40103BMS consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102BMS is config ured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary counter. Each type has c

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INTERSIL

絲印：CD40102B；Package：SOP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 頁(yè)數(shù)：22 Pages

TI

德州儀器

絲印：CD40102B；Package：SOP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 頁(yè)數(shù)：22 Pages

TI

德州儀器