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          首頁 >CD4>規(guī)格書列表

          型號下載 訂購功能描述制造商 上傳企業(yè)LOGO

          CD40103BMS

          CMOS 8-Stage Presettable Synchronous Down Counters

          Description CD40102BMS and CD40103BMS consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102BMS is config ured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary counter. Each type has c

          文件:166.83 Kbytes 頁數(shù):13 Pages

          INTERSIL

          CD40103BNSR

          絲?。?a target="_blank" title="Marking" href="/cd40103b/marking.html">CD40103B;Package:SOP;CMOS 8-Stage Presettable Synchronous Down Counters

          Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

          文件:1.00908 Mbytes 頁數(shù):22 Pages

          TI

          德州儀器

          CD40103BNSR.A

          絲?。?a target="_blank" title="Marking" href="/cd40103b/marking.html">CD40103B;Package:SOP;CMOS 8-Stage Presettable Synchronous Down Counters

          Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

          文件:1.00908 Mbytes 頁數(shù):22 Pages

          TI

          德州儀器

          CD40103BPW

          絲?。?a target="_blank" title="Marking" href="/cm0103b/marking.html">CM0103B;Package:TSSOP;CMOS 8-Stage Presettable Synchronous Down Counters

          Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

          文件:1.00908 Mbytes 頁數(shù):22 Pages

          TI

          德州儀器

          CD40103BPW.A

          絲?。?a target="_blank" title="Marking" href="/cm0103b/marking.html">CM0103B;Package:TSSOP;CMOS 8-Stage Presettable Synchronous Down Counters

          Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

          文件:1.00908 Mbytes 頁數(shù):22 Pages

          TI

          德州儀器

          CD40104BMS

          CMOS 4-Bit Bidirectional Universal Shift Register

          Description The CD40104BMS is a universal shift register featuring parallel inputs, parallel outputs, SHIFT RIGHT and SHIFT LEFT serial inputs, and a high impedance third output state allowing the device to be used in bus organized systems. In the parallel load mode (S0 and S1 are high), dat

          文件:129.88 Kbytes 頁數(shù):10 Pages

          INTERSIL

          CD40105

          CMOS FIFO Register

          Features ? 4 Bits x 16 Words ? High Voltage Type (20V Rating) ? Independent Asynchronous Inputs and Outputs ? 3-State Outputs ? Expandable in Either Direction ? Status Indicators on Input and Output ? Reset Capability ? Standardized Symmetrical Output Characteristics ? 1

          文件:116.54 Kbytes 頁數(shù):10 Pages

          INTERSIL

          CD40105B

          CMOS FIFO Register

          Features: # Independent asynchronous inputs and outputs ? 3state outputs ? Expandable in sither direction = Status indicators on input and output ? Reset capability ? Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

          文件:512.51 Kbytes 頁數(shù):11 Pages

          TI

          德州儀器

          CD40105BE

          絲?。?a target="_blank" title="Marking" href="/cd40105be/marking.html">CD40105BE;Package:PDIP;CMOS FIFO Register

          Features: # Independent asynchronous inputs and outputs ? 3state outputs ? Expandable in sither direction = Status indicators on input and output ? Reset capability ? Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

          文件:512.51 Kbytes 頁數(shù):11 Pages

          TI

          德州儀器

          CD40105BE.A

          絲?。?a target="_blank" title="Marking" href="/cd40105be/marking.html">CD40105BE;Package:PDIP;CMOS FIFO Register

          Features: # Independent asynchronous inputs and outputs ? 3state outputs ? Expandable in sither direction = Status indicators on input and output ? Reset capability ? Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

          文件:512.51 Kbytes 頁數(shù):11 Pages

          TI

          德州儀器

          晶體管資料

          • 型號:

            CD400A

          • 別名:

            三極管、晶體管、晶體三極管

          • 生產(chǎn)廠家:

          • 制作材料:

          • 性質(zhì):

            射頻/高頻放大 (HF)_靜噪放大 (LN)_寬頻帶放大

          • 封裝形式:

            直插封裝

          • 極限工作電壓:

            15V

          • 最大電流允許值:

            0.03A

          • 最大工作頻率:

            <1MHZ或未知

          • 引腳數(shù):

            3

          • 可代換的型號:

          • 最大耗散功率:

            0.2W

          • 放大倍數(shù):

          • 圖片代號:

            A-11

          • vtest:

            15

          • htest:

            999900

          • atest:

            0.03

          • wtest:

            0.2

          技術(shù)參數(shù)

          • Function:

            NOR gates/Inverters

          • Description:

            Dual 3-input NOR gate and inverter

          • VCC (V):

            3.0?-?15.0

          • Logic switching levels:

            CMOS

          • Tamb (°C):

            -40~125

          • Nr of pins:

            14

          • Package:

            DIP14/SOP14/TSSOP14

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          更多CD4供應(yīng)商 更新時(shí)間2025-8-28 16:26:00
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