1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

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1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

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1.2 GHz時(shí)鐘分配IC，PLL內(nèi)核，分頻器，延遲調(diào)整，8路輸出

AD9510提供多路輸出時(shí)鐘分配功能，并集成一個(gè)片內(nèi)鎖相環(huán)(PLL)內(nèi)核。它具有低抖動(dòng)和低相位噪聲特性，能夠極大地提升數(shù)據(jù)轉(zhuǎn)換器的時(shí)鐘性能。4路獨(dú)立的LVPECL時(shí)鐘輸出和4路LVDS時(shí)鐘輸出工作頻率分別為1.2 GHz和800 MHz?？蛇x的CMOS時(shí)鐘輸出工作頻率為250 MHz。\n\n PLL部分由可編程參考分頻器(R)、低噪聲鑒頻鑒相器(PFD)、精密電荷泵(CP)和可編程反饋分頻器(N)組成。將外部VCXO或VCO連接到CLK2和CLK2B引腳時(shí)，最高達(dá)1.6 GHz的PLL輸出頻率可以與輸入?yún)⒖糝EFIN同步。\n\n 時(shí)鐘分配部分提供LVPECL輸出和可編程 ? 低相位噪聲鎖相環(huán)內(nèi)核\n? 最高250 MHz的基準(zhǔn)輸入頻率\n\n? 可編程雙模預(yù)分頻器\n\n? 可編程電荷泵(CP)電流\n\n? 獨(dú)立的CP電源(VCPS)可擴(kuò)展調(diào)整范圍\n\n\n\n\n? 兩路1.6 GHz差分時(shí)鐘輸入\n\n? 8個(gè)可編程分頻器，1至32整數(shù)分頻比\n\n? 用于輸出到輸出延遲粗調(diào)的相位選擇\n\n? 4路獨(dú)立的1.2 GHz LVPECL輸出\n? 加性輸出抖動(dòng)：225 fs rms\n\n\n\n\n? 4路獨(dú)立的800 MHz低壓差模信號(hào)\n? (LVDS)或250 MHz互補(bǔ)金屬氧化物半導(dǎo)體\n\n? (CMOS)時(shí)鐘輸出\n\n? 加性輸出抖動(dòng)：2;

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1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：597.01 Kbytes 頁(yè)數(shù)：60 Pages

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1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：597.01 Kbytes 頁(yè)數(shù)：60 Pages

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亞德諾

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：597.01 Kbytes 頁(yè)數(shù)：60 Pages

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亞德諾

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：597.01 Kbytes 頁(yè)數(shù)：60 Pages

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亞德諾

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：597.01 Kbytes 頁(yè)數(shù)：60 Pages

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亞德諾

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：597.01 Kbytes 頁(yè)數(shù)：60 Pages

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1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

文件：886.11 Kbytes 頁(yè)數(shù)：56 Pages

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