絲?。?a target="_blank" title="Marking" href="/tbd/marking.html">TBD；Package：SOIC；CLOCK SYNCHRONIZER AND MULTIPLIER

? On-chip Phase-Locked Loop for clocks synchronization. ? Synchronizes frequencies up to 107 MHz (output) @ 5.0 V ? ±1ns skew (max) between input & output clocks @ 5.0 V ? Can recover poor duty cycle clocks ? CLK1 to CLK2 skew controlled to within ±1ns @ 5.0 V ? 3.0 - 5.5 V supply range ?

文件：484.66 Kbytes 頁(yè)數(shù)：13 Pages

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絲?。?a target="_blank" title="Marking" href="/tbd/marking.html">TBD；Package：SOIC；CLOCK SYNCHRONIZER AND MULTIPLIER

? On-chip Phase-Locked Loop for clocks synchronization. ? Synchronizes frequencies up to 107 MHz (output) @ 5.0 V ? ±1ns skew (max) between input & output clocks @ 5.0 V ? Can recover poor duty cycle clocks ? CLK1 to CLK2 skew controlled to within ±1ns @ 5.0 V ? 3.0 - 5.5 V supply range ?

文件：484.66 Kbytes 頁(yè)數(shù)：13 Pages

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The IDT9170B generates an output clock which is synchronized to a given continuous input clock with zero delay (±1ns at 5 V VDD). Using IDT's proprietary phase-locked loop (PLL) analog CMOS technology, the IDT9170B is useful for regenerating clocks in high speed systems where skew is a major concern On-chip Phase-Locked Loop for clocks synchronization.\nSynchronizes frequencies up to 107 MHz (output) @ 5.0 V\n±1ns skew (max) between input & output clocks @ 5.0 V\nCan recover poor duty cycle clocks\nCLK1 to CLK2 skew controlled to within ±1ns @ 5.0 V\n3.0 - 5.5 V supply range\nLow power CMOS tec;

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