LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

文件：1.25545 Mbytes 頁(yè)數(shù)：19 Pages

IDT

Low Skew, 1-to-12 LVCMOS/ LVTTL Clock Multiplier/ Zero Delay Buffer

文件：467.82 Kbytes 頁(yè)數(shù)：20 Pages

IDT

LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

文件：1.25545 Mbytes 頁(yè)數(shù)：19 Pages

IDT

絲印：ICS87973DYILF；Package：LQFP；Low Skew, 1-to-12 LVCMOS / LVTTL Clock Mult iplier/Zero Delay Buffer

文件：264.19 Kbytes 頁(yè)數(shù)：17 Pages

IDT

絲?。?a target="_blank" title="Marking" href="/ics87973dyilf/marking.html">ICS87973DYILF；Package：LQFP；Low Skew, 1-to-12 LVCMOS / LVTTL Clock Mult iplier/Zero Delay Buffer

文件：264.19 Kbytes 頁(yè)數(shù)：17 Pages

IDT

Low Skew, 1-to-12 LVCMOS/ LVTTL Clock Multiplier/ Zero Delay Buffer

文件：467.82 Kbytes 頁(yè)數(shù)：20 Pages

IDT

Fully integrated PLL

文件：400.81 Kbytes 頁(yè)數(shù)：19 Pages

IDT

Low Skew, 1-to-12 LVCMOS/ LVTTL Clock Multiplier/ Zero Delay Buffer

文件：467.82 Kbytes 頁(yè)數(shù)：20 Pages

IDT

1:12 LVCMOS Clock Generator

The 87973I is a LVCMOS/LVTTL clock generator from IDT. The 87973I has three selectable inputs and provides fourteen LVCMOS/LVTTL outputs. The 87973I is a highly flexible device. The three selectable inputs (1 differential and 2 single ended inputs) are often used in systems requiring redundant clock ? Fully integrated PLL\n? twelve clock outputs, one feedback, one sync\n? CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL\n? Output frequency range: 8.33MHz to 125MHz\n? Output skew: 550ps (maximum)\n? Full 3.3V supply voltage\n? Available in lead-free RoHS compliant package\n? Com;

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Low Skew, 1-to-12 LVCMOS/LVTTL Clock Multiplier/Zero Delay Buffer

The 87973I-147 is a LVCMOS/LVTTL clock generator and a member of the HiPerClockS? family of High Performance Clock Solutions from IDT. The 87973I-147 has three selectable inputs and provides 14 LVCMOS/LVTTL outputs. The 87973I-147 is a highly flexible device. The three selectable inputs (1 different Fully integrated PLL\nFourteen LVCMOS/LVTTL outputs to include: twelve clocks, one feedback, one sync\nSelectable differential CLK, nCLK inputs or LVCMOS/LVTTL reference clock inputs\nCLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL\nCLK, nCLK pair can accept the following different;

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