Low Skew, 1-to-12 LVCMOS / LVTTL Clock Multiplier/Zero Delay Buffer

FEATURES ? Fully integrated PLL ? Fourteen LVCMOS/LVTTL outputs; twelve clock outputs, one feedback, one sync ? Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs ? CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL ? CLK, nCLK pair can accept the following differential

文件：432.88 Kbytes 頁數(shù)：18 Pages

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瑞薩

Low Skew, 1-to-12 LVCMOS / LVTTL Clock Mult iplier/Zero Delay Buffer

文件：264.19 Kbytes 頁數(shù)：17 Pages

IDT

絲?。?a target="_blank" title="Marking" href="/ics87973di147l/marking.html">ICS87973DI147L；Package：LQFP；Low Skew, 1-to-12 LVCMOS/ LVTTL Clock Multiplier/ Zero Delay Buffer

Features ? Fully integrated PLL ? Fourteen LVCMOS/LVTTL outputs to include: twelve clocks, one feedback, one sync ? Selectable differential CLK, nCLK inputs or LVCMOS/LVTTL reference clock inputs ? CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL ? CLK, nCLK pair can accep

文件：663.57 Kbytes 頁數(shù)：21 Pages

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瑞薩

絲印：ICS87973DI147L；Package：LQFP；Low Skew, 1-to-12 LVCMOS/ LVTTL Clock Multiplier/ Zero Delay Buffer

Features ? Fully integrated PLL ? Fourteen LVCMOS/LVTTL outputs to include: twelve clocks, one feedback, one sync ? Selectable differential CLK, nCLK inputs or LVCMOS/LVTTL reference clock inputs ? CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL ? CLK, nCLK pair can accep

文件：663.57 Kbytes 頁數(shù)：21 Pages

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瑞薩

絲?。?a target="_blank" title="Marking" href="/ics87973dyilf/marking.html">ICS87973DYILF；Package：LQFP；Low Skew, 1-to-12 LVCMOS / LVTTL Clock Multiplier/Zero Delay Buffer

FEATURES ? Fully integrated PLL ? Fourteen LVCMOS/LVTTL outputs; twelve clock outputs, one feedback, one sync ? Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs ? CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL ? CLK, nCLK pair can accept the following differential

文件：432.88 Kbytes 頁數(shù)：18 Pages

RENESAS

瑞薩

絲?。?a target="_blank" title="Marking" href="/ics87973dyilf/marking.html">ICS87973DYILF；Package：LQFP；Low Skew, 1-to-12 LVCMOS / LVTTL Clock Multiplier/Zero Delay Buffer

FEATURES ? Fully integrated PLL ? Fourteen LVCMOS/LVTTL outputs; twelve clock outputs, one feedback, one sync ? Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs ? CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL ? CLK, nCLK pair can accept the following differential

文件：432.88 Kbytes 頁數(shù)：18 Pages

RENESAS

瑞薩

Low Skew, 1-to-12 LVCMOS/ LVTTL Clock Multiplier/ Zero Delay Buffer

Features ? Fully integrated PLL ? Fourteen LVCMOS/LVTTL outputs to include: twelve clocks, one feedback, one sync ? Selectable differential CLK, nCLK inputs or LVCMOS/LVTTL reference clock inputs ? CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL ? CLK, nCLK pair can accep

文件：663.57 Kbytes 頁數(shù)：21 Pages

RENESAS

瑞薩

LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

文件：1.25545 Mbytes 頁數(shù)：19 Pages

IDT

LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

文件：1.25545 Mbytes 頁數(shù)：19 Pages

IDT

Low Skew, 1-to-12 LVCMOS/ LVTTL Clock Multiplier/ Zero Delay Buffer

文件：467.82 Kbytes 頁數(shù)：20 Pages

IDT