1:1 Differential-to-LVDS Zero Delay Clock Generator

Features ? One differential LVDS output designed to meet or exceed the requirements of ANSI TIA/EIA-644 One differential feedback output pair ? Differential CLK, nCLK input pair ? CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? Output

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RENESAS

瑞薩

Differential CLK

文件：322.91 Kbytes 頁數(shù)：19 Pages

IDT

1:1, Differential-to-LVDS Zero Delay Clock Generator

The 8745B-21 is a highly versatile 1:1 LVDS Clock Generator. The 8745B-21 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The Reference Divider, Feedback Divider and Output Divider are each program ·One differential LVDS output designed to meet or exceed the requirements of ANSI TIA/EIA-644 One differential feedback output pair\n·Differential CLK, nCLK input pair\n·CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL\n·Output frequency range: 31;

Renesas

瑞薩

QFN-40

REALTEK

瑞昱

上傳：深圳市禾興威科技有限公司

MOLEX/莫仕

CONNECTOR

科耐沃爾

上傳：深圳市長旗科技有限公司