首頁 >8745BMI-21>規(guī)格書列表
| 型號 | 下載 訂購 | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
8745BMI-21 | 絲印：ICS8745BMI-21；Package：SOIC；1:1 Differential-to-LVDS Zero Delay Clock Generator Features ? One differential LVDS output designed to meet or exceed the requirements of ANSI TIA/EIA-644 One differential feedback output pair ? Differential CLK, nCLK input pair ? CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? Output 文件：620.39 Kbytes 頁數(shù)：21 Pages | RENESAS 瑞薩 | RENESAS | |
8745BMI-21 | 1:1 Differential-to-LVDS Zero Delay Clock Generator 文件：423.95 Kbytes 頁數(shù)：20 Pages | IDT | IDT | |
絲?。?a target="_blank" title="Marking" href="/ics8745bmi-21lf/marking.html">ICS8745BMI-21LF；Package：SOIC；1:1 Differential-to-LVDS Zero Delay Clock Generator Features ? One differential LVDS output designed to meet or exceed the requirements of ANSI TIA/EIA-644 One differential feedback output pair ? Differential CLK, nCLK input pair ? CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? Output 文件：620.39 Kbytes 頁數(shù)：21 Pages | RENESAS 瑞薩 | RENESAS | ||
絲印：ICS8745BMI-21LF；Package：SOIC；1:1 Differential-to-LVDS Zero Delay Clock Generator Features ? One differential LVDS output designed to meet or exceed the requirements of ANSI TIA/EIA-644 One differential feedback output pair ? Differential CLK, nCLK input pair ? CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? Output 文件：620.39 Kbytes 頁數(shù)：21 Pages | RENESAS 瑞薩 | RENESAS | ||
絲?。?a target="_blank" title="Marking" href="/ics8745bmi-21/marking.html">ICS8745BMI-21；Package：SOIC；1:1 Differential-to-LVDS Zero Delay Clock Generator Features ? One differential LVDS output designed to meet or exceed the requirements of ANSI TIA/EIA-644 One differential feedback output pair ? Differential CLK, nCLK input pair ? CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? Output 文件：620.39 Kbytes 頁數(shù)：21 Pages | RENESAS 瑞薩 | RENESAS | ||
1:1 Differential-to-LVDS Zero Delay Clock Generator 文件：423.95 Kbytes 頁數(shù)：20 Pages | IDT | IDT | ||
1:1 Differential-to-LVDS Zero Delay Clock Generator 文件：423.95 Kbytes 頁數(shù)：20 Pages | IDT | IDT | ||
1:1 Differential-to-LVDS Zero Delay Clock Generator 文件：423.95 Kbytes 頁數(shù)：20 Pages | IDT | IDT | ||
IC CLK GEN 1:1 DIFF-LVDS 20-SOIC | Renesas 瑞薩 | Renesas | ||
Package：20-SOIC（0.295"，7.50mm 寬）；包裝：卷帶（TR） 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：IC CLK GEN 1:1 DIFF-LVDS 20-SOIC | Renesas Electronics America Inc | Renesas Electronics America Inc |
技術(shù)參數(shù)
- PLL：
帶旁路
- 輸入：
HCSL，LVDS，LVHSTL，LVPECL，SSTL
- 輸出：
LVDS
- 電路數(shù)：
1
- 比率 - 輸入：
輸出
- 差分 - 輸入：
輸出
- 頻率 - 最大值：
700MHz
- 分頻器/倍頻器：
是/是
- 電壓 - 電源：
3.135 V ~ 3.465 V
- 工作溫度：
-40°C ~ 85°C
- 安裝類型：
表面貼裝
- 封裝/外殼：
20-SOIC（0.295\，7.50mm 寬）
- 供應(yīng)商器件封裝：
20-SOIC
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
IDT, Integrated Device Technol |
24+ |
20-SOIC |
56200 |
一級代理/放心采購 |
詢價 | ||
IDT |
1931+ |
N/A |
1186 |
加我qq或微信，了解更多詳細信息,體驗一站式購物 |
詢價 | ||
IDT |
25+ |
SOP-20 |
1001 |
就找我吧!--邀您體驗愉快問購元件! |
詢價 | ||
IDT |
22+ |
NA |
1186 |
加我QQ或微信咨詢更多詳細信息, |
詢價 | ||
Renesas Electronics America In |
25+ |
20-SOIC(0.295 7.50mm 寬) |
9350 |
獨立分銷商 公司只做原裝 誠心經(jīng)營 免費試樣正品保證 |
詢價 | ||
Renesas |
25+ |
電聯(lián)咨詢 |
7800 |
公司現(xiàn)貨,提供拆樣技術(shù)支持 |
詢價 | ||
INTEGRATEDCIRCUITSYSTEMS |
23+ |
NA |
111 |
專做原裝正品,假一罰百! |
詢價 | ||
IDT |
23+ |
LQFP |
5000 |
原廠授權(quán)代理,海外優(yōu)勢訂貨渠道?？商峁┐罅繋齑?詳 |
詢價 | ||
IDT |
兩年內(nèi) |
N/A |
13521 |
原裝現(xiàn)貨,實單價格可談 |
詢價 | ||
IDT |
2025+ |
LQFP |
2500 |
詢價 |
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