Standard distributor without bus termination

文件：98.43 Kbytes 頁數：4 Pages

WEIDMULLER

魏德米勒

絲?。?a target="_blank" title="Marking" href="/8714h/marking.html">8714H；Package：HTQFP；DRV871x-Q1 Automotive Multi-Channel Smart Half-Bridge Gate Drivers With Wide Common Mode Inline Current Sense Amplifiers

1 Features ? AEC-Q100 qualified for automotive applications: – Temperature grade 1: –40°C to +125°C, TA ? Multi-channel half-bridge gate drivers – Pin to pin 4 and 8 half-bridge driver variants – 4.9-V to 37-V (40-V abs. max) operating range – 4 PWM inputs with output mapping – Tripler char

文件：4.84834 Mbytes 頁數：178 Pages

TI

德州儀器

絲印：8714S；Package：HTQFP；DRV871x-Q1 Automotive Multi-Channel Smart Half-Bridge Gate Drivers With Wide Common Mode Inline Current Sense Amplifiers

1 Features ? AEC-Q100 qualified for automotive applications: – Temperature grade 1: –40°C to +125°C, TA ? Multi-channel half-bridge gate drivers – Pin to pin 4 and 8 half-bridge driver variants – 4.9-V to 37-V (40-V abs. max) operating range – 4 PWM inputs with output mapping – Tripler char

文件：4.84834 Mbytes 頁數：178 Pages

TI

德州儀器

FemtoClock? Zero Delay Buffer/Clock Generator For PCI Express? And Ethernet

The 8714008I is Zero-Delay Buffer/Frequency Multiplier with eight differential HCSL output pairs, and uses external feedback (differential feedback input and output pairs) for \"zero delay\" clock regeneration. In PCI Express? and Ethernet applications, 100MHz and 125MHz are the most commonly used r ·Eight 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications\n·One differential clock input pair CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, LVHSTL, HCSL\n·One M-LVDS I/O pair (MLVDS/nMLVDS)\n·Outpu;

Renesas

瑞薩

多導線電纜

LAPP

纜普

多導線電纜

LAPP

纜普

包裝：散裝 類別：標簽，標志，護欄，標識 標簽 描述：1-1/2\

Brady Corporation

包裝：散裝 類別：標簽，標志，護欄，標識 標簽 描述：1-1/2\

Brady Corporation