8714008I中文資料FemtoClock? Zero Delay Buffer/Clock Generator For PCI Express? And Ethernet 數(shù)據(jù)手冊(cè)Renesas規(guī)格書(shū)

| 廠(chǎng)商型號(hào) |
8714008I |
| 功能描述 | FemtoClock? Zero Delay Buffer/Clock Generator For PCI Express? And Ethernet |
| 制造商 | Renesas Renesas Technology Corp |
| 中文名稱(chēng) | 瑞薩 瑞薩科技有限公司 |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2026-1-21 14:31:00 |
| 人工找貨 | 8714008I價(jià)格和庫(kù)存,歡迎聯(lián)系客服免費(fèi)人工找貨 |
相關(guān)芯片規(guī)格書(shū)
更多8714008I規(guī)格書(shū)詳情
描述 Description
The 8714008I is Zero-Delay Buffer/Frequency Multiplier with eight differential HCSL output pairs, and uses external feedback (differential feedback input and output pairs) for \"zero delay\" clock regeneration. In PCI Express? and Ethernet applications, 100MHz and 125MHz are the most commonly used reference clock frequencies and each of the eight output pairs can be independently set for either 100MHz or 125MHz. With an output frequency range of 98MHz to 165MHz, the device is also suitable for use in a variety of other applications such as Fibre Channel (106.25MHz) and XAUI (156.25MHz). The M-LVDS Input/Output pair is useful in backplane applications when the reference clock can either be local (on the same board as the 8714008I) or remote via a backplane connector. In output mode, an input from a local reference clock applied to the CLK/nCLK input pins is translated to M-LVDS and driven out to the MLVDS/nMLVDS pins. In input mode, the internal M-LVDS driver is placed in Hi-Z state using the OE_MLVDS pin and MLVDS/nMLVDS pin then becomes an input (e.g. from a backplane). The 8714008I uses very low phase noise FemtoClock technology, thus making it ideal for such applications as PCI Express? Generation 1 and 2 as well as for Gigabit Ethernet, Fibre Channel, and 10 Gigabit Ethernet. It is packaged in a 56-VFQFN package (8mm x 8mm).
特性 Features
·Eight 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications
·One differential clock input pair CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, LVHSTL, HCSL
·One M-LVDS I/O pair (MLVDS/nMLVDS)
·Output frequency range: 98MHz - 165MHz
·Input frequency range: 19.6MHz - 165MHz
·VCO range: 490MHz - 660MHz
·PCI Express? (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant
·External feedback for \"zero delay\" clock regeneration
·RMS phase jitter @ 125MHz (1.875MHz – 20MHz): 0.57ps (typical)
·Full 3.3V supply mode
·-40°C to 85°C ambient operating temperature
·Available in lead-free (RoHS 6) package
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
NU |
24+ |
185 |
詢(xún)價(jià) | ||||
MOLEX |
24+/25+ |
471 |
原裝正品現(xiàn)貨庫(kù)存價(jià)優(yōu) |
詢(xún)價(jià) | |||
AMIS |
24+ |
QFP |
35200 |
一級(jí)代理/放心采購(gòu) |
詢(xún)價(jià) | ||
25+ |
5000 |
百分百原裝正品 真實(shí)公司現(xiàn)貨庫(kù)存 本公司只做原裝 可 |
詢(xún)價(jià) | ||||
ACES |
2450+ |
Connector |
6540 |
只做原裝正品假一賠十為客戶(hù)做到零風(fēng)險(xiǎn)!! |
詢(xún)價(jià) | ||
AMI |
23+ |
QFP-100 |
5000 |
原廠(chǎng)授權(quán)代理,海外優(yōu)勢(shì)訂貨渠道??商峁┐罅繋?kù)存,詳 |
詢(xún)價(jià) | ||
TE/泰科 |
24+ |
49374 |
原廠(chǎng)現(xiàn)貨渠道 |
詢(xún)價(jià) | |||
ACES |
25+ |
37965 |
普通 |
詢(xún)價(jià) | |||
ACES |
2019+ |
Connector |
1000 |
進(jìn)口原裝現(xiàn)貨假一賠萬(wàn)力挺實(shí)單 |
詢(xún)價(jià) | ||
REI |
16+ |
原廠(chǎng)封裝 |
10000 |
全新原裝正品,代理優(yōu)勢(shì)渠道供應(yīng),歡迎來(lái)電咨詢(xún) |
詢(xún)價(jià) |

