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          首頁 >8701>規(guī)格書列表

          型號下載 訂購功能描述制造商 上傳企業(yè)LOGO

          87016AYLF

          絲?。?a target="_blank" title="Marking" href="/ics87016aylf/marking.html">ICS87016AYLF;Package:LQFP;Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

          FEATURES ? Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) ? Selectable differential CLK1, nCLK1 or LVCMOS clock input ? CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? CLK0 supports the following input types: LVCMOS, LVTTL ? Maxi

          文件:865.7 Kbytes 頁數(shù):16 Pages

          RENESAS

          瑞薩

          87016AYLF/W

          絲印:ICS87016AYLF;Package:LQFP;Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

          FEATURES ? Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) ? Selectable differential CLK1, nCLK1 or LVCMOS clock input ? CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? CLK0 supports the following input types: LVCMOS, LVTTL ? Maxi

          文件:865.7 Kbytes 頁數(shù):16 Pages

          RENESAS

          瑞薩

          87016AYLFSLASHW

          絲?。?a target="_blank" title="Marking" href="/ics87016aylf/marking.html">ICS87016AYLF;Package:LQFP;Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

          FEATURES ? Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) ? Selectable differential CLK1, nCLK1 or LVCMOS clock input ? CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? CLK0 supports the following input types: LVCMOS, LVTTL ? Maxi

          文件:865.7 Kbytes 頁數(shù):16 Pages

          RENESAS

          瑞薩

          87016AYLFT

          絲?。?a target="_blank" title="Marking" href="/ics87016aylf/marking.html">ICS87016AYLF;Package:LQFP;Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

          FEATURES ? Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) ? Selectable differential CLK1, nCLK1 or LVCMOS clock input ? CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? CLK0 supports the following input types: LVCMOS, LVTTL ? Maxi

          文件:865.7 Kbytes 頁數(shù):16 Pages

          RENESAS

          瑞薩

          87016I

          Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

          Features ? Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) ? Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock input ? CLK1, CLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? CLK0 supports the following input types: LVCMOS, LVTTL ? Max

          文件:898.68 Kbytes 頁數(shù):16 Pages

          RENESAS

          瑞薩

          8701CYILF

          絲?。?a target="_blank" title="Marking" href="/ics8701cyilf/marking.html">ICS8701CYILF;Package:LQFP;Low Skew, ÷1, ÷2 Clock Generator

          FEATURES ? Twenty LVCMOS outputs, 7Ω typical output impedance ? LVCMOS / LVTTL clock input ? Maximum input frequency: 250MHz ? Bank enable logic allows unused banks to be disabled in reduced fanout applications ? Bank skew: 200ps ? Output skew: 250ps ? Multiple frequency skew: 300ps ? Par

          文件:341.61 Kbytes 頁數(shù):15 Pages

          RENESAS

          瑞薩

          8701CYILFT

          絲印:ICS8701CYILF;Package:LQFP;Low Skew, ÷1, ÷2 Clock Generator

          FEATURES ? Twenty LVCMOS outputs, 7Ω typical output impedance ? LVCMOS / LVTTL clock input ? Maximum input frequency: 250MHz ? Bank enable logic allows unused banks to be disabled in reduced fanout applications ? Bank skew: 200ps ? Output skew: 250ps ? Multiple frequency skew: 300ps ? Par

          文件:341.61 Kbytes 頁數(shù):15 Pages

          RENESAS

          瑞薩

          8701CYLF

          絲印:ICS8701CYLF;Package:LQFP;Low Skew, ÷1, ÷2 LVCMOS/LVTTL Clock Generator

          FEATURES ? Twenty LVCMOS outputs, 7Ω typical output impedance ? One LVCMOS/LVTTL clock input ? Maximum output frequency: 250MHz ? Bank enable logic allows unused banks to be disabled in reduced fanout applications ? Output skew: 250ps (maximum) ? Part-to-part skew: 600ps (maximum) ? Bank s

          文件:373.8 Kbytes 頁數(shù):14 Pages

          RENESAS

          瑞薩

          8701CYLFT

          絲?。?a target="_blank" title="Marking" href="/ics8701cylf/marking.html">ICS8701CYLF;Package:LQFP;Low Skew, ÷1, ÷2 LVCMOS/LVTTL Clock Generator

          FEATURES ? Twenty LVCMOS outputs, 7Ω typical output impedance ? One LVCMOS/LVTTL clock input ? Maximum output frequency: 250MHz ? Bank enable logic allows unused banks to be disabled in reduced fanout applications ? Output skew: 250ps (maximum) ? Part-to-part skew: 600ps (maximum) ? Bank s

          文件:373.8 Kbytes 頁數(shù):14 Pages

          RENESAS

          瑞薩

          8701I

          Low Skew, ÷1, ÷2 Clock Generator

          FEATURES ? Twenty LVCMOS outputs, 7Ω typical output impedance ? LVCMOS / LVTTL clock input ? Maximum input frequency: 250MHz ? Bank enable logic allows unused banks to be disabled in reduced fanout applications ? Bank skew: 200ps ? Output skew: 250ps ? Multiple frequency skew: 300ps ? Par

          文件:341.61 Kbytes 頁數(shù):15 Pages

          RENESAS

          瑞薩

          產(chǎn)品屬性

          • 產(chǎn)品編號:

            8701

          • 制造商:

            Keystone Electronics

          • 類別:

            五金件,緊固件,配件 > 螺絲,螺栓

          • 包裝:

            散裝

          • 類型:

            有肩螺釘

          • 螺釘頭類型:

            旋鈕

          • 驅(qū)動類型:

            開槽型

          • 螺紋規(guī)格:

            #4-40

          • 頭部直徑:

            0.320"(8.13mm)

          • 頭部高度:

            0.188"(4.78mm)3/16"

          • 長度 - 頭部以下:

            0.781"(19.84mm)25/32"

          • 長度 - 總體:

            0.968"(24.59mm)

          • 材料:

            不銹鋼

          • 描述:

            SHOULDER SCREW KNOB SLOTTED 4-40

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