Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

Features ? Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) ? Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock input ? CLK1, CLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? CLK0 supports the following input types: LVCMOS, LVTTL ? Max

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Maximum output frequency

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Low Skew,1-to-16 LVCMOS/LVTTL Clock Generator

The 87016I is a low skew, 1:16 LVCMOS/LVTTL Clock Generator and is a member of the HiPerClockS family of High Performance Clock Solutions. The device has 4 banks of 4 outputs and each bank can be independently selected for ÷1 or ÷2 frequency operation. Each bank also has its own power supply pins so ? Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)\n? CLK1, CLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL\n? Maximum output frequency: 250MHz\n? Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V operation\n? Output skew: 170ps (maxim;

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Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

Features ? Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) ? Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock input ? CLK1, CLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? CLK0 supports the following input types: LVCMOS, LVTTL ? Max

文件：898.68 Kbytes 頁數(shù)：16 Pages

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Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

Features ? Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) ? Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock input ? CLK1, CLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? CLK0 supports the following input types: LVCMOS, LVTTL ? Max

文件：898.68 Kbytes 頁數(shù)：16 Pages

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