絲?。?a target="_blank" title="Marking" href="/85411alf/marking.html">85411ALF；Package：SOIC；Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES ? Two differential LVDS outputs ? One differential CLK, nCLK clock input ? CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? Maximum output frequency: 650MHz ? Translates any single ended input signal to LVDS levels with resistor

文件：386.95 Kbytes 頁數(shù)：16 Pages

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Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES ? Two differential LVDS outputs ? One differential CLK, nCLK clock input ? CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? Maximum output frequency: 650MHz ? Translates any single ended input signal to LVDS levels with resistor

文件：386.46 Kbytes 頁數(shù)：16 Pages

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絲印：85411AIL；Package：SOIC；Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

文件：228.99 Kbytes 頁數(shù)：15 Pages

IDT

絲?。?a target="_blank" title="Marking" href="/85411ail/marking.html">85411AIL；Package：SOIC；Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

文件：228.99 Kbytes 頁數(shù)：15 Pages

IDT

絲?。?a target="_blank" title="Marking" href="/85411alf/marking.html">85411ALF；Package：SOIC；Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

文件：230.58 Kbytes 頁數(shù)：15 Pages

IDT

Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

文件：228.99 Kbytes 頁數(shù)：15 Pages

IDT

絲?。?a target="_blank" title="Marking" href="/85411000/marking.html">85411000；Package：SMA；Diode 600 V 1.5A Surface Mount DO-214AC, SMA

Features Controlled avalanche characteristic High average forward current Compliant to RoHS (exemp. 7a), REACH, Conflict Minerals 1)

文件：768.6 Kbytes 頁數(shù)：3 Pages

DIOTEC

德歐泰克

絲?。?a target="_blank" title="Marking" href="/85411000/marking.html">85411000；Package：SMA；Diode 600 V 1.5A Surface Mount DO-214AC, SMA

Features Controlled avalanche characteristic High average forward current Compliant to RoHS (exemp. 7a), REACH, Conflict Minerals 1)

文件：768.6 Kbytes 頁數(shù)：3 Pages

DIOTEC

德歐泰克

2.5V Differential LVDS Clock Buffer

The 854110I is a high-performance differential LVDS clock fanout buffer. The device is designed for signal fanout of high-frequency, low phase-noise clock signals. The selected differential input signal is distributed to ten differential LVDS outputs. The 854110I is characterized to operate from a 2 ·Two differential input reference clocks\n·Differential pair can accept the following differential input levels: LVPECL, LVDS\n·Ten LVDS outputs\n·Maximum clock frequency: 200MHz\n·Output slew rate control\n·Fail-safe differential inputs\n·LVCMOS interface levels for all control inputs\n·Output skew;

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Low Skew,1-to-2 Differential-ToLVDS Fanout Buffer

The 85411I is a low skew, high performance 1-to-2 Differential-to-LVDS Fanout Buffer and a member of the family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels.The 85411I is characterized to operate from a 3.3V power supply. Guarant ? Two differential LVDS outputs\n? One differential CLK, nCLK clock input\n? CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL\n? Maximum output frequency: 650MHz\n? Translates any single ended input signal to LVDS levels with resistor bias on nCLK i;

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