絲?。?strong>8101；Package：32LdQFN；Adaptive Digital DC/DC PWM Controller with Auto Compensation

文件：1.57394 Mbytes 頁數(shù)：36 Pages

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瑞薩

絲?。?strong>8101；Package：32LdQFN；Adaptive Digital DC/DC PWM Controller with Auto Compensation

文件：1.57394 Mbytes 頁數(shù)：36 Pages

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瑞薩

絲?。?strong>8101；Package：32LdQFN；Adaptive Digital DC/DC PWM Controller with Auto Compensation

文件：1.57394 Mbytes 頁數(shù)：36 Pages

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瑞薩

絲印：8101602EA；Package：CDIP；CMOS Presettable Up/Down Counter

Features: ? Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ? Binary or d

文件：1.02221 Mbytes 頁數(shù)：22 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/8101801ea/marking.html">8101801EA；Package：CDIP(J)；CD405xB CMOS Single 8-Channel Analog Multiplexer or Demultiplexer With Logic-Level Conversion

1 Features ? Wide range of digital and analog signal levels: – Digital: 3V to 20V – Analog: ≤ 20VP-P ? Single supply range : 3V to 20V (performance degrades for VDD

文件：1.65707 Mbytes 頁數(shù)：40 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/8101801ea/marking.html">8101801EA；Package：CDIP；CD405xB CMOS Single 8-Channel Analog Multiplexer or Demultiplexer With Logic-Level Conversion

1 Features ? Wide range of digital and analog signal levels: – Digital: 3 V to 20 V – Analog: ≤ 20 VP-P ? Low ON resistance, 125 Ω (typical) over 15 VP-P signal input range for VDD – VEE = 18 V ? High OFF resistance, channel leakage of ±100 pA (typical) at VDD – VEE = 18 V ? Logic-level co

文件：1.72366 Mbytes 頁數(shù)：48 Pages

TI

德州儀器

絲印：8101801EA；Package：CDIP；CD405xB CMOS Single 8-Channel Analog Multiplexer or Demultiplexer With Logic-Level Conversion

1 Features ? Wide range of digital and analog signal levels: – Digital: 3 V to 20 V – Analog: ≤ 20 VP-P ? Low ON resistance, 125 Ω (typical) over 15 VP-P signal input range for VDD – VEE = 18 V ? High OFF resistance, channel leakage of ±100 pA (typical) at VDD – VEE = 18 V ? Logic-level co

文件：1.66329 Mbytes 頁數(shù)：42 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/8101602ea/marking.html">8101602EA；Package：CDIP；CMOS Presettable Up/Down Counter

Features: ? Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ? Binary or d

文件：1.02221 Mbytes 頁數(shù)：22 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/8101602ea/marking.html">8101602EA；Package：CDIP；CMOS Presettable Up/Down Counter

Features: ? Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ? Binary or d

文件：1.02221 Mbytes 頁數(shù)：22 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/8101701ea/marking.html">8101701EA；Package：CDIP；CMOS 4-Stage Parallel In/Parallel Out Shift Register

Features: ? 4-Stage clocked shift operation # Synchronous parallel entry on all 4 stages a JK inputs on first stage ? Asynchronous True/Complement control on all outputs ? Static flip-flop operation; Master-slave configuration ? Buffered inputs and outputs ? High speed — 12

文件：710.52 Kbytes 頁數(shù)：17 Pages

TI

德州儀器