Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs

General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly relate

文件：67.29 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

LOW POWER SCHOTTKY

The SN74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive-going edge of

文件：102.75 Kbytes 頁數(shù)：8 Pages

ONSEMI

安森美半導(dǎo)體

Dual D-type Positive Edge-triggered Flip-Flops(With Preset and Clear)

Dual D-type Positive Edge-triggered Flip-Flops(With Preset and Clear)

文件：69.14 Kbytes 頁數(shù)：6 Pages

HITACHIHitachi Semiconductor

日立日立公司

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54/74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs. Information at input D is transferred

文件：73.39 Kbytes 頁數(shù)：3 Pages

MOTOROLA

摩托羅拉

Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs

文件：136.42 Kbytes 頁數(shù)：6 Pages

NSC

國半

Dual D-Type Positive Edge - Triggered Flip-Flop

文件：240.62 Kbytes 頁數(shù)：6 Pages

SYC

LOW POWER SCHOTTKY

ONSEMI

安森美半導(dǎo)體

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

文件：699.19 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

54LS74A

文件：264.57 Kbytes 頁數(shù)：2 Pages

ETCList of Unclassifed Manufacturers

未分類制造商

Dual D-type Positive Edge-triggered Flip-Flops (with Preset and Clear)

文件：102.82 Kbytes 頁數(shù)：8 Pages

RENESAS

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