| 型號(hào) | 下載 訂購(gòu) | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
74HC112D | Dual JK flip-flop with set and reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Asynchronous set and reset ? Output capability: standard ? ICC category: flip 文件:106.77 Kbytes 頁數(shù):15 Pages | PHI PHI | PHI | |
74HC112D | Dual JK flip-flop with set and reset; negative-edge trigger 1. General description The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate indepen 文件:267.28 Kbytes 頁數(shù):16 Pages | NEXPERIA 安世 | NEXPERIA | |
Dual JK flip-flop with set and reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Asynchronous set and reset ? Output capability: standard ? ICC category: flip 文件:106.77 Kbytes 頁數(shù):15 Pages | PHI PHI | PHI | ||
74HC112D | Dual JK flip-flop with set and reset; negative-edge trigger The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. T ? Input levels:? For 74HC112: CMOS level\n? For 74HCT112: TTL level\n\n? Asynchronous set and reset\n? Specified in compliance with JEDEC standard no. 7A\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V\n\n? Multiple package options\n? Specified from -40 °C to +8; | Nexperia 安世 | Nexperia | |
J-K Type Flip-Flops dual JK flip-flop with set and reset; negative-edge trigger - The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous act ·Input levels:·For 74HC112: CMOS level\n·For 74HCT112: TTL level; | Nexperia 安世 | Nexperia | ||
Package:16-SOIC(0.154",3.90mm 寬);包裝:卷帶(TR)剪切帶(CT)Digi-Reel? 得捷定制卷帶 功能:設(shè)置(預(yù)設(shè))和復(fù)位 類別:集成電路(IC) 觸發(fā)器 描述:IC FF JK TYPE DUAL 1BIT 16SO | Nexperia USA Inc. | Nexperia USA Inc. | ||
Package:16-SSOP(0.209",5.30mm 寬);包裝:卷帶(TR) 功能:設(shè)置(預(yù)設(shè))和復(fù)位 類別:集成電路(IC) 觸發(fā)器 描述:IC FF JK TYPE DUAL 1BIT 16SSOP | Nexperia USA Inc. | Nexperia USA Inc. | ||
Package:16-SSOP(0.209",5.30mm 寬);包裝:卷帶(TR) 功能:設(shè)置(預(yù)設(shè))和復(fù)位 類別:集成電路(IC) 觸發(fā)器 描述:IC FF JK TYPE DUAL 1BIT 16SSOP | Nexperia USA Inc. | Nexperia USA Inc. |
技術(shù)參數(shù)
- VCC (V):
2.0?-?6.0
- Logic switching levels:
CMOS
- Output drive capability (mA):
± 5.2
- tpd (ns):
15
- fmax (MHz):
66
- Power dissipation considerations:
low
- Tamb (°C):
-40~125
- Rth(j-a) (K/W):
76
- Ψth(j-top) (K/W):
2.4
- Rth(j-c) (K/W):
34
- Package name:
SO16
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
NEXPERIA/安世 |
25+ |
SOT109-1 |
600000 |
NEXPERIA/安世全新特價(jià)74HC112D即刻詢購(gòu)立享優(yōu)惠#長(zhǎng)期有排單訂 |
詢價(jià) | ||
PHI |
2021+ |
SOP16 |
9000 |
原裝現(xiàn)貨,隨時(shí)歡迎詢價(jià) |
詢價(jià) | ||
Nexperia |
25+ |
SOIC-16 |
7786 |
正規(guī)渠道,免費(fèi)送樣。支持賬期,BOM一站式配齊 |
詢價(jià) | ||
PHI |
24+ |
SOP |
97 |
詢價(jià) | |||
PHI |
05+ |
原廠原裝 |
50051 |
只做全新原裝真實(shí)現(xiàn)貨供應(yīng) |
詢價(jià) | ||
PHI |
25+ |
SOP16 |
1497 |
百分百原裝正品 真實(shí)公司現(xiàn)貨庫存 本公司只做原裝 可 |
詢價(jià) | ||
恩XP |
2016+ |
SOP-16 |
3500 |
只做原裝,假一罰十,公司可開17%增值稅發(fā)票! |
詢價(jià) | ||
原廠正品 |
23+ |
SO-16 |
5000 |
原裝正品,假一罰十 |
詢價(jià) | ||
恩XP |
16+ |
NA |
8800 |
誠(chéng)信經(jīng)營(yíng) |
詢價(jià) | ||
ph |
24+ |
N/A |
6980 |
原裝現(xiàn)貨,可開13%稅票 |
詢價(jià) |
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