Dual JK flip-flop with set and reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Asynchronous set and reset ? Output capability: standard ? ICC category: flip

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PHI

PHI

J-K Type Flip-Flops

dual JK flip-flop with set and reset; negative-edge trigger - The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous act ·Input levels:·For 74HC112: CMOS level\n·For 74HCT112: TTL level;

Nexperia

安世

Package：16-SSOP（0.209"，5.30mm 寬）；包裝：卷帶（TR） 功能：設(shè)置（預(yù)設(shè)）和復(fù)位 類(lèi)別：集成電路（IC） 觸發(fā)器 描述：IC FF JK TYPE DUAL 1BIT 16SSOP

Nexperia USA Inc.

Package：16-SSOP（0.209"，5.30mm 寬）；包裝：卷帶（TR） 功能：設(shè)置（預(yù)設(shè)）和復(fù)位 類(lèi)別：集成電路（IC） 觸發(fā)器 描述：IC FF JK TYPE DUAL 1BIT 16SSOP

Nexperia USA Inc.