| 型號(hào) | 下載 訂購(gòu) | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J 文件：259.73 Kbytes 頁(yè)數(shù)：15 Pages | NEXPERIA 安世 | NEXPERIA | ||
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp 文件：259.39 Kbytes 頁(yè)數(shù)：15 Pages | NEXPERIA 安世 | NEXPERIA | ||
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp 文件：259.39 Kbytes 頁(yè)數(shù)：15 Pages | NEXPERIA 安世 | NEXPERIA | ||
Dual JK flip-flop with set and reset; positive-edge-trigger 1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of 文件：271.64 Kbytes 頁(yè)數(shù)：16 Pages | NEXPERIA 安世 | NEXPERIA | ||
Dual JK flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) 文件：65.67 Kbytes 頁(yè)數(shù)：9 Pages | PHI PHI | PHI | ||
High Speed CMOS Logic Features Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS109. 文件：303.58 Kbytes 頁(yè)數(shù)：6 Pages | SS | SS | ||
High Speed CMOS Logic Features Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS109. 文件：303.58 Kbytes 頁(yè)數(shù)：6 Pages | SS | SS | ||
Dual JK flip-flop with set and reset; positive-edge-trigger 1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of 文件：271.64 Kbytes 頁(yè)數(shù)：16 Pages | NEXPERIA 安世 | NEXPERIA | ||
Dual JK flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) 文件：65.67 Kbytes 頁(yè)數(shù)：9 Pages | PHI PHI | PHI | ||
Dual JK flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) 文件：65.67 Kbytes 頁(yè)數(shù)：9 Pages | PHI PHI | PHI |
技術(shù)參數(shù)
- VCC (V)：
2.0?-?6.0
- Logic switching levels：
CMOS
- Output drive capability (mA)：
± 5.2
- tpd (ns)：
16
- fmax (MHz)：
78
- Power dissipation considerations：
low
- Tamb (°C)：
-40~125
- Rth(j-a) (K/W)：
87
- Ψth(j-top) (K/W)：
6.5
- Rth(j-c) (K/W)：
45
- Package name：
SO14
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
25+ |
5000 |
公司現(xiàn)貨庫(kù)存 |
詢(xún)價(jià) | ||||
TMS |
06+ |
SOIC |
1000 |
全新原裝 絕對(duì)有貨 |
詢(xún)價(jià) | ||
HAR |
24+ |
SOP |
988 |
詢(xún)價(jià) | |||
HIT |
24+ |
N/A |
25843 |
公司原廠(chǎng)原裝現(xiàn)貨假一罰十!特價(jià)出售!強(qiáng)勢(shì)庫(kù)存! |
詢(xún)價(jià) | ||
MOT |
93+ |
SOIC-14/3.9mm |
4 |
原裝現(xiàn)貨海量庫(kù)存歡迎咨詢(xún) |
詢(xún)價(jià) | ||
ST |
25+ |
SOP-14 |
2987 |
只售原裝自家現(xiàn)貨!誠(chéng)信經(jīng)營(yíng)!歡迎來(lái)電! |
詢(xún)價(jià) | ||
Nexperia |
24+ |
SOP |
20000 |
一級(jí)代理進(jìn)口原裝現(xiàn)貨假一賠十 |
詢(xún)價(jià) | ||
SGS |
23+ |
SMD-SO14 |
9856 |
原裝正品,假一罰百! |
詢(xún)價(jià) | ||
M |
24+ |
SOP14 |
20000 |
全新原廠(chǎng)原裝，進(jìn)口正品現(xiàn)貨，正規(guī)渠道可含稅??！ |
詢(xún)價(jià) | ||
HIT |
24+ |
N/A |
6540 |
原裝現(xiàn)貨/歡迎來(lái)電咨詢(xún) |
詢(xún)價(jià) |
相關(guān)規(guī)格書(shū)
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- NE5532
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相關(guān)庫(kù)存
更多- COS5532
- NE5532
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- MAX232E
- MAX232E
- MAX232ESE
- NE5533
- SI7970DP
- SI7958DP
- SI7913DN
- SI7942DP
- SI7911DN
- SI7900EDN
- SI7922DN
- SI7946DP
- SI7945DP
- SI7921DN
- SI7905DN
- SI7938DP
- SI7925DN
- SI7948DP
- SI7946ADP
- SE1
- PI7C8150B
- PI7C8150DNDE
- PERICOMPI7C8150
- WNS40H100C
- WNS40H100CB
- TD62308
- TD62308APG
- TD62308AFG
- GRM21BR71H104JA11#
- TL074
