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    首頁(yè) >74HC10>規(guī)格書列表

    型號(hào)下載 訂購(gòu)功能描述制造商 上傳企業(yè)LOGO

    74HC10

    Triple 3-input NAND gate

    GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. FEATURES ? Output capability: standard ? ICC categ

    文件:34.29 Kbytes 頁(yè)數(shù):5 Pages

    PHI

    PHI

    PHI

    74HC10

    Triple 3-input NAND gate

    1. General description The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits ? Complies with JEDEC standard JESD7A ? Input levels: ? For74HC10

    文件:224.64 Kbytes 頁(yè)數(shù):11 Pages

    NEXPERIA

    安世

    74HC107

    Dual JK flip-flop with reset; negative-edge trigger

    GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

    文件:53.67 Kbytes 頁(yè)數(shù):7 Pages

    PHI

    PHI

    PHI

    74HC107

    Dual JK flip-flop with reset; negative-edge trigger

    1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J

    文件:259.73 Kbytes 頁(yè)數(shù):15 Pages

    NEXPERIA

    安世

    74HC107D

    Dual JK flip-flop with reset; negative-edge trigger

    1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J

    文件:259.73 Kbytes 頁(yè)數(shù):15 Pages

    NEXPERIA

    安世

    74HC107D

    Dual JK flip-flop with reset; negative-edge trigger

    GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

    文件:53.67 Kbytes 頁(yè)數(shù):7 Pages

    PHI

    PHI

    PHI

    74HC107DB

    Dual JK flip-flop with reset; negative-edge trigger

    GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

    文件:53.67 Kbytes 頁(yè)數(shù):7 Pages

    PHI

    PHI

    PHI

    74HC107D-Q100

    Dual JK flip-flop with reset; negative-edge trigger

    1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp

    文件:259.39 Kbytes 頁(yè)數(shù):15 Pages

    NEXPERIA

    安世

    74HC107N

    Dual JK flip-flop with reset; negative-edge trigger

    GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

    文件:53.67 Kbytes 頁(yè)數(shù):7 Pages

    PHI

    PHI

    PHI

    74HC107PW

    Dual JK flip-flop with reset; negative-edge trigger

    GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

    文件:53.67 Kbytes 頁(yè)數(shù):7 Pages

    PHI

    PHI

    PHI

    技術(shù)參數(shù)

    • VCC (V):

      2.0?-?6.0

    • Logic switching levels:

      CMOS

    • Output drive capability (mA):

      ± 5.2

    • tpd (ns):

      16

    • fmax (MHz):

      78

    • Power dissipation considerations:

      low

    • Tamb (°C):

      -40~125

    • Rth(j-a) (K/W):

      87

    • Ψth(j-top) (K/W):

      6.5

    • Rth(j-c) (K/W):

      45

    • Package name:

      SO14

    供應(yīng)商型號(hào)品牌批號(hào)封裝庫(kù)存備注價(jià)格
    25+
    5000
    公司現(xiàn)貨庫(kù)存
    詢價(jià)
    TMS
    06+
    SOIC
    1000
    全新原裝 絕對(duì)有貨
    詢價(jià)
    HAR
    24+
    SOP
    988
    詢價(jià)
    HIT
    24+
    N/A
    25843
    公司原廠原裝現(xiàn)貨假一罰十!特價(jià)出售!強(qiáng)勢(shì)庫(kù)存!
    詢價(jià)
    MOT
    93+
    SOIC-14/3.9mm
    4
    原裝現(xiàn)貨海量庫(kù)存歡迎咨詢
    詢價(jià)
    ST
    25+
    SOP-14
    2987
    只售原裝自家現(xiàn)貨!誠(chéng)信經(jīng)營(yíng)!歡迎來電!
    詢價(jià)
    Nexperia
    24+
    SOP
    20000
    一級(jí)代理進(jìn)口原裝現(xiàn)貨假一賠十
    詢價(jià)
    SGS
    23+
    SMD-SO14
    9856
    原裝正品,假一罰百!
    詢價(jià)
    M
    24+
    SOP14
    20000
    全新原廠原裝,進(jìn)口正品現(xiàn)貨,正規(guī)渠道可含稅!!
    詢價(jià)
    HIT
    24+
    N/A
    6540
    原裝現(xiàn)貨/歡迎來電咨詢
    詢價(jià)
    更多74HC10供應(yīng)商 更新時(shí)間2026-1-22 16:43:00

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