Octal Registered Transceiver

General Description The F543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction

文件：67.51 Kbytes 頁數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

Octal registered transceiver, non-inverting 3-State

DESCRIPTION The 74F543 and 74F544 Octal Registered Transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are provided for each register to permit independent control of in

文件：119.39 Kbytes 頁數(shù)：16 Pages

PHI

PHI

Octal latched transceiver with dual enable; 3-state

General description The 74F543 octal latched transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch enable (LEAB, LEBA) and output enable (OEAB, OEBA) inputs are provided for each register to permit independent control of data t

文件：99.26 Kbytes 頁數(shù)：15 Pages

恩XP

Octal latched transceiver with dual enable; 3-state

General description\nThe 74F543 octal latched transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch enable (LEAB, LEBA) and output enable (OEAB, OEBA) inputs are provided for each register to permit independent control of data trans ■ Combines 74F245 and 74F373 type functions in one device\n■ 8-bit octal transceiver with D-type latch\n■ Back-to-back registers for storage\n■ Separate controls for data flow in each direction\n■ A output capability: +20 mA to ?3 mA\n■ B output capability: +64 mA to ?15 mA\n■ 3-state outputs for bu;

恩XP

Octal Registered Transceiver

General Description\nThe F543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction o ■ 8-bit octal transceiver\n■ Back-to-back registers for storage\n■ Separate controls for data flow in each direction\n■ A outputs sink 24 mA\n■ B outputs sink 64 mA;

ONSEMI

安森美半導(dǎo)體

Octal registered transceiver, non-inverting 3-State

DESCRIPTION The 74F543 and 74F544 Octal Registered Transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are provided for each register to permit independent control of in

文件：119.39 Kbytes 頁數(shù)：16 Pages

PHI

PHI

Octal Registered Transceiver

General Description The F543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction

文件：67.51 Kbytes 頁數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

Octal Registered Transceiver

General Description The F543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction

文件：67.51 Kbytes 頁數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

Octal Registered Transceiver

General Description The F543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction

文件：67.51 Kbytes 頁數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

Octal Registered Transceiver

文件：78.98 Kbytes 頁數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體