Octal D-Type Flip-Flop with 3-STATE Outputs

General Description The 74F564 is a high-speed, low power octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is sorted in the flip-flops on the LOW-to-HIGH Clock (CP) transition. This device is functionally identi

文件：48.19 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

Octal D-Type Flip-Flop with 3-STATE Outputs

文件：63.79 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

Package：20-DIP（0.300"，7.62mm）；包裝：袋 功能：標(biāo)準(zhǔn) 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 8BIT 20DIP

ONSEMI

安森美半導(dǎo)體

Octal D-Type Flip-Flop with 3-STATE Outputs

文件：63.79 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

Octal D-Type Flip-Flop with 3-STATE Outputs

General Description The 74F564 is a high-speed, low power octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is sorted in the flip-flops on the LOW-to-HIGH Clock (CP) transition. This device is functionally identi

文件：48.19 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

Octal D flip-flop 3-State

DESCRIPTION The 74F564 has a broadside pinout configuration to facilitate PC board layout and allows easy interface with microprocessors. It is an 8-bit, edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the clock (CP

文件：80.45 Kbytes 頁數(shù)：10 Pages

PHI

PHI