MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D3444)

FUNCTIONAL DESCRIPTION The 3D3444 device is a small, versatile, quad 4-bit programmable monolithic delay line. Delay values, programmed via the serial interface, can be independently varied over 15 equal steps. The step size (in ns) is determined by the device dash number. Each input is reproduce

文件：313.47 Kbytes 頁數(shù)：6 Pages

DATADELAY

MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D3444)

FUNCTIONAL DESCRIPTION The 3D3444 device is a small, versatile, quad 4-bit programmable monolithic delay line. Delay values, programmed via the serial interface, can be independently varied over 15 equal steps. The step size (in ns) is determined by the device dash number. Each input is reproduce

文件：313.47 Kbytes 頁數(shù)：6 Pages

DATADELAY

MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D3444)

FUNCTIONAL DESCRIPTION The 3D3444 device is a small, versatile, quad 4-bit programmable monolithic delay line. Delay values, programmed via the serial interface, can be independently varied over 15 equal steps. The step size (in ns) is determined by the device dash number. Each input is reproduce

文件：313.47 Kbytes 頁數(shù)：6 Pages

DATADELAY

MONOLITHIC MANCHESTER ENCODER

FUNCTIONAL DESCRIPTION The 3D3521 is a monolithic CMOS Manchester Encoder. The clock and data, present at the unit input, are combined into a single bi-phaselevel signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is repre

文件：229.94 Kbytes 頁數(shù)：4 Pages

DATADELAY

MONOLITHIC MANCHESTER ENCODER

FUNCTIONAL DESCRIPTION The 3D3521 is a monolithic CMOS Manchester Encoder. The clock and data, present at the unit input, are combined into a single bi-phaselevel signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is repre

文件：229.94 Kbytes 頁數(shù)：4 Pages

DATADELAY

MONOLITHIC MANCHESTER ENCODER

FUNCTIONAL DESCRIPTION The 3D3521 is a monolithic CMOS Manchester Encoder. The clock and data, present at the unit input, are combined into a single bi-phaselevel signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is repre

文件：229.94 Kbytes 頁數(shù)：4 Pages

DATADELAY

MONOLITHIC MANCHESTER ENCODER

FUNCTIONAL DESCRIPTION The 3D3521 is a monolithic CMOS Manchester Encoder. The clock and data, present at the unit input, are combined into a single bi-phaselevel signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is repre

文件：229.94 Kbytes 頁數(shù)：4 Pages

DATADELAY

MONOLITHIC MANCHESTER ENCODER

FUNCTIONAL DESCRIPTION The 3D3521 is a monolithic CMOS Manchester Encoder. The clock and data, present at the unit input, are combined into a single bi-phaselevel signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is repre

文件：229.94 Kbytes 頁數(shù)：4 Pages

DATADELAY

MONOLITHIC MANCHESTER ENCODER

FUNCTIONAL DESCRIPTION The 3D3521 is a monolithic CMOS Manchester Encoder. The clock and data, present at the unit input, are combined into a single bi-phaselevel signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is repre

文件：229.94 Kbytes 頁數(shù)：4 Pages

DATADELAY

MONOLITHIC MANCHESTER DECODER

FUNCTIONAL DESCRIPTION The 3D3522 product family consists of monolithic CMOS Manchester Decoders. The unit accepts at the RX input a bi-phase-level, embedded-clock signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is repr

文件：257.67 Kbytes 頁數(shù)：4 Pages

DATADELAY