絲?。?strong>Y4；Package：SOT1089；Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：290.66 Kbytes 頁數(shù)：19 Pages

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絲?。?strong>Y4；Package：SOT1116；Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：290.66 Kbytes 頁數(shù)：19 Pages

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絲?。?strong>Y4；Package：SOT1203；Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：290.66 Kbytes 頁數(shù)：19 Pages

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絲?。?strong>Y4；Package：SOT1116；Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：278.15 Kbytes 頁數(shù)：18 Pages

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絲?。?strong>Y4；Package：SOT1203；Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：278.15 Kbytes 頁數(shù)：18 Pages

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絲?。?strong>Y4；Package：SOT-23；300mW Surface Mount Zener Diodes

Features ? Silicon Planar Power Zener Diodes ? 350mW Power Dissipation ? Standard Zener Voltage Tolerance is ± 5 ? Ideally Suited for Automated Assembly Processes ? High temperature soldering guaranteed: 260 °C / 10 seconds in reflow soldering process ? RoHS Compliant

文件：153.69 Kbytes 頁數(shù)：5 Pages

TAITRON

絲?。?strong>Y4；Package：SOT-23；Zener Votage Regulator Diodes

GENERAL DATA APPLICABLE TO ALL SERIES IN THISH GROUP Zener Voltage Regulator Diodes MAXIMUM CASE TEMPERATURE FOR SOLDERING PURPOSES: 260°C for 10 seconds

文件：1.10793 Mbytes 頁數(shù)：4 Pages

SKTECHNOLGYSHIKE Electronics

時科廣東時科微實(shí)業(yè)有限公司

絲?。?strong>Y4；Package：SOT-23；Silicon Planar Zener Diodes

■ Silicon Planar Zener Diodes This series of Zener diodes is offered in the convenient, surface mount plastic SOT-23 package. These devices are designed to provide voltage regulation with minimum space requirement. They are well suited for applications such as cellular phones, hand held portables

文件：900.32 Kbytes 頁數(shù)：4 Pages

YFWDIODE

佑風(fēng)微

絲?。?strong>Y4；Package：SOT-23；Small Signal Zener Diodes

FEATURES ? These diodes are also available in other case styles and other configurations including: the SOD-123 case with type designation BZT52 series, the zener diode common anode configuration in the SOT-23 case with type designation AZ23 series and the zener diode common cathode configuration

文件：136.2 Kbytes 頁數(shù)：9 Pages

VISHAYVishay Siliconix

威世威世科技公司

絲?。?strong>Y4；Package：SOT-23；Small Signal Zener Diodes

FEATURES ? These diodes are also available in other case styles and other configurations including: the SOD-123 case with type designation BZT52 series, the zener diode common anode configuration in the SOT-23 case with type designation AZ23 series and the zener diode common cathode configuration

文件：452 Kbytes 頁數(shù)：10 Pages

VISHAYVishay Siliconix

威世威世科技公司