UPD720100A中文資料USB2.0 HOST CONTROLLER數(shù)據(jù)手冊Renesas規(guī)格書

描述 Description

The μPD720100A complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for high-speed signaling and works up to 480 Mbps. The μPD720100A is integrated three host controller cores with PCI interface and USB2.0 transceivers into a single chip. Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing. μPD720100A User’s Manual: S15534EFEATURES
? Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)
? Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
? Compliant with Enhanced Host Controller Interface Specification for USB Rev 0.95
? PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI
host controller core for high-speed signaling.
? Root hub with five (max.) downstream facing ports which are shared by OHCI and EHCI host controller core
? All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction.
? Configurable number of downstream facing ports (2 to 5)
? 32-bit 33 MHz host interface compliant to PCI Specification release 2.2.
? Supports PCI Mobile Design Guide Revision 1.1.
? Supports PCI-Bus Power Management Interface Specification release 1.1.
? PCI Bus bus-master access
? System clock is generated by 30 MHz X’tal or 48 MHz clock input.
? Operational registers direct-mapped to PCI memory space
? Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard implementation.
? 3.3 V power supply, PCI signal pins have 5 V tolerant circuit.

特性 Features

? Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)
? Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
? Compliant with Enhanced Host Controller Interface Specification for USB Rev 0.95
? PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI
host controller core for high-speed signaling.
? Root hub with five (max.) downstream facing ports which are shared by OHCI and EHCI host controller core
? All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction.
? Configurable number of downstream facing ports (2 to 5)
? 32-bit 33 MHz host interface compliant to PCI Specification release 2.2.
? Supports PCI Mobile Design Guide Revision 1.1.
? Supports PCI-Bus Power Management Interface Specification release 1.1.
? PCI Bus bus-master access
? System clock is generated by 30 MHz X’tal or 48 MHz clock input.
? Operational registers direct-mapped to PCI memory space
? Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard implementation.
? 3.3 V power supply, PCI signal pins have 5 V tolerant circuit.