VR5500??64-/32-BIT MICROPROCESSOR

DESCRIPTION The μPD30550 (VR5500) is a member of the VRSeries? of RISC (Reduced Instruction Set Computer) microprocessors. It is a high-performance 64-/32-bit microprocessor that employs the RISC architecture developed by MIPS?. The VR5500 allowsselection of a 64-bit or 32-bit bus width for

文件：949.43 Kbytes 頁數(shù)：27 Pages

NEC

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VR5500? 64-/32-BIT MICROPROCESSOR

DESCRIPTION\nThe μPD30550 (VR5500) is a member of the VRSeries? of RISC (Reduced Instruction Set Computer) microprocessors. It is a high-performance 64-/32-bit microprocessor that employs the RISC architecture developed by MIPS?.\nThe VR5500 allowsselection of a 64-bit or 32-bit bus width for the sy ? MIPS 64-bit RISC architecture\n? High-speed operation processing\n? Two-waysuperscaler super pipeline\n? 300 MHz product:? 603 MIPS\n? 400 MHz product:? 804 MIPS\n? High-speed translation lookaside buffer (TLB) (48 entries)\n?Address space\n? Physical:? 36 bits (64-bit bus selected) 32 bits (32-bi;

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VR5500??64-/32-BIT MICROPROCESSOR

DESCRIPTION The μPD30550 (VR5500) is a member of the VRSeries? of RISC (Reduced Instruction Set Computer) microprocessors. It is a high-performance 64-/32-bit microprocessor that employs the RISC architecture developed by MIPS?. The VR5500 allowsselection of a 64-bit or 32-bit bus width for

文件：949.43 Kbytes 頁數(shù)：27 Pages

NEC

瑞薩

VR5500??64-/32-BIT MICROPROCESSOR

DESCRIPTION The μPD30550 (VR5500) is a member of the VRSeries? of RISC (Reduced Instruction Set Computer) microprocessors. It is a high-performance 64-/32-bit microprocessor that employs the RISC architecture developed by MIPS?. The VR5500 allowsselection of a 64-bit or 32-bit bus width for

文件：949.43 Kbytes 頁數(shù)：27 Pages

NEC

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