Reconfigurable FPGA with 48 x TTL IO 32 x 16 bit Analog In / 8 x 16 bit Analog Out

Application Information The TXMC635 is a standard single-width Switched Mezzanine Card (XMC) compatible module providing a user configurable XC6SLX45T-2 or XC6SLX100T-2 Xilinx Spartan-6 FPGA. 48 ESD-protected TTL lines provide a flexible digital interface. All I/O lines are individually programm

文件：292.46 Kbytes 頁(yè)數(shù)：3 Pages

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Reconfigurable FPGA with Analog Input (16 bit), Analog Output (16 bit) and TTL I/O

The TXMC635 is a standard single-width Switched Mezzanine Card (XMC) compatible module providing a user configurable XC6SLX45T-2 or XC6SLX100T-2 AMD Spartan ? 6 FPGA.\n\n48 ESD-protected TTL lines provide a flexible digital interface. All I/O lines are individually programmable as input or output. S ? Standard XMC module\n? 128?Mbyte, 16?bit wide DDR3 SDRAM\n? I/O direction is individually programmable\n? ESD protected;

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Reconfigurable FPGA with 48 x TTL IO 32 x 16 bit Analog In / 8 x 16 bit Analog Out

Application Information The TXMC635 is a standard single-width Switched Mezzanine Card (XMC) compatible module providing a user configurable XC6SLX45T-2 or XC6SLX100T-2 Xilinx Spartan-6 FPGA. 48 ESD-protected TTL lines provide a flexible digital interface. All I/O lines are individually programm

文件：292.46 Kbytes 頁(yè)數(shù)：3 Pages

TEWS

Reconfigurable FPGA with 48 x TTL IO 32 x 16 bit Analog In / 8 x 16 bit Analog Out

Application Information The TXMC635 is a standard single-width Switched Mezzanine Card (XMC) compatible module providing a user configurable XC6SLX45T-2 or XC6SLX100T-2 Xilinx Spartan-6 FPGA. 48 ESD-protected TTL lines provide a flexible digital interface. All I/O lines are individually programm

文件：292.46 Kbytes 頁(yè)數(shù)：3 Pages

TEWS

Reconfigurable FPGA with 48 x TTL IO 32 x 16 bit Analog In / 8 x 16 bit Analog Out

Application Information The TXMC635 is a standard single-width Switched Mezzanine Card (XMC) compatible module providing a user configurable XC6SLX45T-2 or XC6SLX100T-2 Xilinx Spartan-6 FPGA. 48 ESD-protected TTL lines provide a flexible digital interface. All I/O lines are individually programm

文件：292.46 Kbytes 頁(yè)數(shù)：3 Pages

TEWS