絲?。?a target="_blank" title="Marking" href="/tser4905/marking.html">TSER4905；Package：VQFN；TSER4905 4K DSI to V3Link Bridge Serializer

1 Features ? Single or dual port MIPI DSI receiver – Compliant to D-PHY v1.2 and DSI v1.3.1 – Packed 16/18/24/30-bit RGB and 16-bit YCbCr – Loosely packed 18-bit RGB and 20-bit 4:2:2 – 1 clock lane and 1-4 configurable data lanes per D-PHY Port – Up to 2.5 Gbps/lane with skew calibration –

文件：424.92 Kbytes 頁數(shù)：7 Pages

TI

德州儀器

TSER4905 4K DSI to V3Link Bridge Serializer

1 Features ? Single or dual port MIPI DSI receiver – Compliant to D-PHY v1.2 and DSI v1.3.1 – Packed 16/18/24/30-bit RGB and 16-bit YCbCr – Loosely packed 18-bit RGB and 20-bit 4:2:2 – 1 clock lane and 1-4 configurable data lanes per D-PHY Port – Up to 2.5 Gbps/lane with skew calibration –

文件：424.92 Kbytes 頁數(shù)：7 Pages

TI

德州儀器

TSER4905 4K DSI to V3Link Bridge Serializer

1 Features ? Single or dual port MIPI DSI receiver – Compliant to D-PHY v1.2 and DSI v1.3.1 – Packed 16/18/24/30-bit RGB and 16-bit YCbCr – Loosely packed 18-bit RGB and 20-bit 4:2:2 – 1 clock lane and 1-4 configurable data lanes per D-PHY Port – Up to 2.5 Gbps/lane with skew calibration –

文件：422.82 Kbytes 頁數(shù)：6 Pages

TI

德州儀器

TSER4905 4K DSI to V3Link Bridge Serializer

1 Features ? Single or dual port MIPI DSI receiver – Compliant to D-PHY v1.2 and DSI v1.3.1 – Packed 16/18/24/30-bit RGB and 16-bit YCbCr – Loosely packed 18-bit RGB and 20-bit 4:2:2 – 1 clock lane and 1-4 configurable data lanes per D-PHY Port – Up to 2.5 Gbps/lane with skew calibration –

文件：424.92 Kbytes 頁數(shù)：7 Pages

TI

德州儀器