8-bit Microcontroller with 2K Bytes In-System Programmable Flash

Features ? Utilizes the AVR? RISC Architecture ? AVR – High-performance and Low-power RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz ? Data and Non-vol

文件：2.29669 Mbytes 頁數(shù)：230 Pages

SYC

Low-Power, Rail-to-Rail In/Out, 500-muV Typical Offset, 1-MHz Operational Amplifier for Cost-Sensitive Systems

文件：2.12707 Mbytes 頁數(shù)：39 Pages

TI

德州儀器

Low-Power, Rail-to-Rail In/Out, 750-uV Typical Offset, 1-MHz Operational Amplifier for Cost-Sensitive Systems

文件：1.96271 Mbytes 頁數(shù)：32 Pages

TI

德州儀器

Low-Power, Rail-to-Rail In/Out, 500-muV Typical Offset, 1-MHz Operational Amplifier for Cost-Sensitive Systems

文件：2.12707 Mbytes 頁數(shù)：39 Pages

TI

德州儀器